74ALVC574PW

74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 8 November 2007 Product data sheet 1. General description The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74ALVC574 is functionally identical to the 74ALVC374, but has a different pin arrangement. 2. Features s s s s s s s Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115A exceeds 200 V NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range Name 74ALVC574D −40 °C to +85 °C SO20 TSSOP20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT360-1 SOT764-1 Type number 74ALVC574PW −40 °C to +85 °C 74ALVC574BQ −40 °C to +85 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 4. Functional diagram 11 1 11 2 3 4 5 6 7 8 9 CP D0 D1 D2 D3 D4 D5 D6 D7 OE 1 mna798 C1 EN 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 8 9 3 4 5 6 7 1D 19 18 17 16 15 14 13 12 mna446 Fig 1. Logic symbol Fig 2. IEC logic symbol 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 FF1 to FF8 3-STATE OUTPUTS Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 11 CP 1 OE mna800 Fig 3. Functional diagram 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 2 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state D0 D1 D2 D3 D4 D5 D6 D7 D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna801 Fig 4. Logic diagram 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 3 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 5. Pinning information 5.1 Pinning 74ALVC574 terminal 1 index area 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 GND(1) GND 10 CP 11 13 Q6 12 Q7 OE 2 3 4 5 6 7 8 9 1 74ALVC574 OE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 CP 001aad095 D0 D1 D2 D3 D4 D5 D6 D7 GND 10 001aad096 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 5.2 Pin description Table 2. Symbol D[0:7] CP OE Q[0:7] VCC GND Pin description Pin 2, 3, 4, 5, 6, 7, 8, 9 11 1 19, 18, 17, 16, 15, 14, 13, 12 20 10 Description data input clock input (LOW to HIGH, edge-triggered) output enable input (active LOW) 3-state flip-flop output supply voltage ground (0 V) 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 4 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 6. Functional description Table 3. Function table[1] Input OE Load and read register Load register and disable outputs [1] Operating mode Internal flip-flop Output CP ↑ ↑ ↑ ↑ Dn l h l h L H L H Qn L H Z Z L L H H H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition Z = high-impedance OFF-state ↑ = LOW to HIGH clock transition 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO Parameter supply voltage input clamping current input voltage output clamping current output voltage VO > VCC or VO < 0 V output HIGH or LOW state output 3-state power-down mode, VCC = 0 V IO ICC IGND Tstg Ptot [1] [2] [3] [2] [1] [2] Conditions VI < 0 V Min −0.5 −50 −0.5 −0.5 −0.5 −0.5 −100 −65 Max +4.6 +4.6 ±50 VCC + 0.5 +4.6 +4.6 ±50 100 +150 500 Unit V mA V mA V V V mA mA mA °C mW output current supply current ground current storage temperature total power dissipation VO = 0 V to VCC Tamb = −40 °C to +85 °C [3] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation. For SO20 packages: above 70 °C derate linearly with 8 mW/K. For TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K. 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 5 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 8. Recommended operating conditions Table 5. Symbol VCC VI VO Recommended operating conditions Parameter supply voltage input voltage output voltage output HIGH or LOW state output 3-state power-down mode; VCC = 0 V Tamb ∆t/∆V ambient temperature input transition rise and fall rate in free air VCC = 1.65 V to 2.7 V VCC = 2.7 V to 3.6 V Conditions Min 1.65 0 0 0 0 −40 0 0 Max 3.6 3.6 VCC 3.6 3.6 +85 20 10 Unit V V V V V °C ns/V ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions Min VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 3.6 V IO = −6 mA; VCC = 1.65 V IO = −12 mA; VCC = 2.3 V IO = −18 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 3.6 V IO = 6 mA; VCC = 1.65 V IO = 12 mA; VCC = 2.3 V IO = 18 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 18 mA; VCC = 3.0 V IO = 24 mA; VCC = 3.0 V II input leakage current VCC = 3.6 V; VI = 3.6 V or GND 0.11 0.17 0.25 0.16 0.23 0.30 ±0.1 0.2 0.3 0.4 0.6 0.4 0.4 0.55 ±5 V V V V V V V µA VCC − 0.2 1.25 1.8 1.7 2.2 2.4 2.2 1.51 2.10 2.01 2.53 2.76 2.68 V V V V V V V 0.65 × VCC 1.7 2.0 −40 °C to +85 °C Typ[1] Max 0.7 0.8 V V V V V Unit 0.35 × VCC V 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 6 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter IOZ IOFF ICC ∆ICC CI [1] Conditions Min VI = VIH or VIL; VCC = 1.65 V to 3.6 V; VO = 3.6 V or GND; VCC = 0 V; VI or VO = 0 V to 3.6 V VCC = 3.6 V; VI = VCC or GND; IO = 0 A per input pin; VCC = 3.0 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A - −40 °C to +85 °C Typ[1] ±0.1 ±0.1 0.2 5 3.5 Max ±10 ±10 10 750 - Unit µA µA µA µA pF OFF-state output current power-off leakage current supply current additional supply current input capacitance All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol tpd Parameter propagation delay Conditions CP to Qn; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V ten enable time OE to Qn; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tdis disable time OE to Qn; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tW pulse width clock HIGH or LOW; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V 3.8 3.3 3.3 3.3 1.1 0.9 0.8 1.2 ns ns ns ns [2] [2] [2] −40 °C to +85 °C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.0 1.5 1.0 Typ[1] 3.1 2.3 2.5 2.5 3.2 2.6 3.2 2.4 3.6 2.3 2.9 2.8 Max 6.4 3.9 3.6 3.6 6.4 4.5 4.6 4.0 7.0 4.4 4.4 4.4 Unit ns ns ns ns ns ns ns ns ns ns ns ns 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 7 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol tsu Parameter set-up time Conditions Dn to CP; see Figure 9 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V th hold time Dn to CP; see Figure 9 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency see Figure 7 VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V CPD power dissipation capacitance per flip-flop; VI = GND to VCC; VCC = 3.3 V outputs HIGH or LOW state outputs 3-state [1] [2] Typical values are measured at Tamb = 25 °C tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs [3] −40 °C to +85 °C Min 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.7 100 100 150 Typ[1] −0.1 0.1 0.3 0.0 −0.1 0.1 0.4 −0.1 200 200 300 21 13 Max - Unit ns ns ns ns ns ns ns ns MHz MHz MHz pF pF [3] 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 8 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 11. Waveforms 1/f max VI CP input GND tW t PHL VOH Qn output VOL VM mna894 VM t PLH Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width, and the maximum frequency Table 8. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VY VOH − 0.15 V VOH − 0.15 V VOH − 0.3 V VOH − 0.3 V Supply voltage VI OE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled mna644 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 8. Enable and disable times 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 9 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state VI CP input GND tsu th VI Dn input GND VM tsu th VM VOH Qn output VOL mna202 VM Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 9. Data set-up and hold times for the Dn input to the CP input 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 10 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Test circuit for switching times Table 9. Test data Input VI 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V VCC VCC 2.7 V 2.7 V tr, tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open tPLZ, tPZL 2VCC 2VCC 6V 6V tPHZ, tPZH GND GND GND GND Supply voltage 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 11 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT163-1 (SO20) 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 12 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT360-1 (TSSOP20) 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 13 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT764-1 (DHVQFN20) 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 14 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 13. Abbreviations Table 10. Acronym CDM DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20071108 Data sheet status Product data sheet Change notice Supersedes 74ALVC574_1 Document ID 74ALVC574_2 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN20 package added. Section 8: derating values added for DHVQFN20 package. Section 12: outline drawing added for DHVQFN20 package. Product specification - 74ALVC574_1 20020304 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 15 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 16 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 November 2007 Document identifier: 74ALVC574_2