74ALVT16374DL,112

74ALVT16374 16-bit edge-triggered D-type flip-flop; 3-state Rev. 04 — 4 July 2005 Product data sheet 1. General description The 74ALVT16374 is a high performance BiCMOS product designed for VCC operation at 2.5 V or 3.3 V with I/O compatibility up to 5 V. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels set up at the D inputs. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 16-bit edge-triggered flip-flop 5 V I/O compatible 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection exceeds 500 mA per JESD78 Electrostatic discharge protection: ◆ MIL STD 883 method 3015: exceeds 2000 V ◆ Machine model: exceeds 200 V 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 3. Quick reference data Table 1: Quick reference data Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.5 V tPLH propagation delay nCP to nQx CL = 50 pF - 2.6 - ns tPHL propagation delay nCP to nQx CL = 50 pF - 2.8 - ns Ci input capacitance nCP and nOE VI = 0 V or VCC - 3 - pF Co output capacitance outputs disabled; VO = 0 V or VCC - 9 - pF ICC supply current outputs disabled - 40 - µA VCC = 3.3 V tPLH propagation delay nCP to nQx CL = 50 pF - 2.1 - ns tPHL propagation delay nCP to nQx CL = 50 pF - 2.3 - ns Ci input capacitance nCP and nOE VI = 0 V or VCC - 3 - pF Co output capacitance outputs disabled; VO = 0 V or VCC - 9 - pF ICC supply current outputs disabled - 40 - µA 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name 74ALVT16374DGG −40 °C to +85 °C 74ALVT16374DL −40 °C to +85 °C Description Version TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 SSOP48 plastic shrink small outline package; 48 leads; body SOT370-1 width 7.5 mm 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 2 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 5. Functional diagram 47 46 44 43 41 40 38 1 1OE 48 1CP 24 2OE 25 2CP 37 1D0 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1CP 1D1 1 1OE 1D2 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2 3 5 6 8 9 11 1D3 1D4 12 1D5 36 35 33 32 30 29 27 1D6 26 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 25 2CP 24 2OE 2D0 2D1 2D2 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2D3 13 14 16 17 19 20 22 23 2D4 001aad246 2D5 2D6 2D7 EN1 C3 EN2 C4 47 3D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 2 4D 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 001aaa254 Fig 1. Logic symbol nD0 Fig 2. IEC logic symbol nD1 D CP nD2 D Q CP nD3 D Q CP nD4 D Q CP nD5 D Q CP nD6 D Q CP nD7 D Q CP D Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 001aac371 Fig 3. Logic diagram 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 3 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 6. Pinning information 6.1 Pinning 1OE 1 48 1CP 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 1Q4 8 42 VCC 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 16374 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 2Q4 19 31 VCC 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2CP 001aad248 Fig 4. Pin configuration 6.2 Pin description Table 3: Pin description Symbol Pin Description 1OE 1 output enable input (active LOW) 1Q0 2 data output 1Q1 3 data output GND 4 ground (0 V) 1Q2 5 data output 1Q3 6 data output VCC 7 supply voltage 1Q4 8 data output 1Q5 9 data output GND 10 ground (0 V) 1Q6 11 data output 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 4 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state Table 3: Pin description Symbol Pin Description 1Q7 12 data output 2Q0 13 data output 2Q1 14 data output GND 15 ground (0 V) 2Q2 16 data output 2Q3 17 data output VCC 18 supply voltage 2Q4 19 data output 2Q5 20 data output GND 21 ground (0 V) 2Q6 22 data output 2Q7 23 data output 2OE 24 output enable input (active LOW) 2CP 25 clock pulse input (active rising edge) 2D7 26 data input 2D6 27 data input GND 28 ground (0 V) 2D5 29 data input 2D4 30 data input VCC 31 supply voltage 2D3 32 data input 2D2 33 data input GND 34 ground (0 V) 2D1 35 data input 2D0 36 data input 1D7 37 data input 1D6 38 data input GND 39 ground (0 V) 1D5 40 data input 1D4 41 data input VCC 42 supply voltage 1D3 43 data input 1D2 44 data input GND 45 ground (0 V) 1D1 46 data input 1D0 47 data input 1CP 48 clock pulse input (active rising edge) 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 5 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 7. Functional description 7.1 Function table Table 4: Function table [1] Input Internal register Output Operating mode nOE nCP nDx L ↑ l L L L ↑ h H H L NC X NC NC hold H NC X NC Z disable outputs H ↑ nDx nDx Z [1] nQx load and read register H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition. 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +4.6 V VI input voltage [1] −0.5 +7.0 V [1] VO output voltage output in OFF-state or HIGH-state −0.5 +7.0 V IIK input diode current VI < 0 V - −50 mA IOK output diode current VO < 0 V - −50 mA IO output current output in LOW-state - 128 mA Tstg storage temperature output in HIGH-state Tj junction temperature −64 mA +150 °C - 150 °C [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9397 750 15193 Product data sheet [2] −65 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 6 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC = 2.5 V ± 0.2 V VCC supply voltage 2.3 - 2.7 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 1.7 - - V VIL LOW-level input voltage - - 0.7 V IOH HIGH-level output current - - −8 mA IOL LOW-level output current - - 8 mA - 24 mA - - 10 ns/V −40 - +85 °C none duty cycle < 50 %; f ≥ 1 kHz ∆t/∆V input transition rise or fall rate Tamb ambient temperature outputs enabled VCC = 3.3 V ± 0.3 V VCC supply voltage 3.0 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current - - −32 mA IOL LOW-level output current none - - 32 mA duty cycle < 50 %; f ≥ 1 kHz - - 64 mA outputs enabled - - 10 ns/V −40 - +85 °C ∆t/∆V input transition rise or fall rate Tamb ambient temperature 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C. Symbol Parameter Conditions Min Typ Max Unit −0.85 −1.2 V - V VCC = 2.5 V ± 0.2 V [1] VIK input diode voltage VCC = 2.3 V; IIK = −18 mA - VOH HIGH-level output voltage VCC = 2.3 V to 3.6 V; IOH = −100 µA VCC − 0.2 VCC VCC = 2.3 V; IOH = −8 mA 1.8 2.1 - V VOL LOW-level output voltage VCC = 2.3 V; IOL = 100 µA - 0.07 0.2 V - 0.3 0.5 V - - 0.55 V VCC = 2.3 V; IOL = 24 mA VRST power-up LOW-state output voltage VCC = 2.7 V; IO = 1 mA; VI = VCC or GND 9397 750 15193 Product data sheet [2] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 7 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C. Symbol Parameter ILI input leakage current control pins I/O data pins Conditions Min Typ Max Unit VCC = 2.7 V; VI = VCC or GND - 0.1 ±1 µA VCC = 0 V or 2.7 V; VI = 5.5 V - 0.1 10 µA VCC = 2.7 V; VI = VCC [3] - 0.1 1 µA VCC = 2.7 V; VI = 0 V [3] - +0.1 −5 µA IOFF output power-down current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 µA IHOLD bus hold current D inputs VCC = 2.3 V; VI = 0.7 V [4] [5] - 90 - µA VCC = 2.3 V; VI = 1.7 V [4] [5] - −10 - µA - 10 125 µA IEX external current into output output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 2.3 V IPU power-up 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care [6] - 1 100 µA IPD power-down 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care [6] - 1 100 µA IOZ 3-state OFF-state output current VCC = 2.7 V; VI = VIH or VIL output HIGH; VO = 2.3 V - 0.5 5 µA output LOW; VO = 0.5 V - +0.5 −5 µA - 0.04 0.1 mA ICC supply current VCC = 2.7 V; VI = VCC or GND; IO = 0 A outputs HIGH-state outputs LOW-state outputs disabled - 2.7 4.5 mA [7] - 0.04 0.1 mA [8] - 0.04 0.4 mA ∆ICC additional supply current per VCC = 2.3 V to 2.7 V; one input at input pin VCC − 0.6 V; other inputs at VCC or GND Ci input capacitance nCP and nOE VI = 0 V or VCC - 3 - pF Co output capacitance outputs disabled; VO = 0 V or VCC - 9 - pF −0.85 VCC = 3.3 V ± 0.3 V [9] VIK input clamp voltage VCC = 3.0 V; IIK = −18 mA - −1.2 V VOH HIGH-level output voltage VCC = 3.0 V to 3.6 V; IOH = −100 µA VCC − 0.2 VCC - V VCC = 3.0 V; IOH = −32 mA 2.0 2.3 - V VCC = 3.0 V; IOL = 100 µA - 0.07 0.2 V VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V - 0.4 0.55 V - - 0.55 V VOL LOW-level output voltage VCC = 3.0 V; IOL = 64 mA VRST power-up LOW-state output voltage VCC = 3.6 V; IO = 1 mA; VI = VCC or GND 9397 750 15193 Product data sheet [2] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 8 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C. Symbol Parameter ILI input leakage current control pins I/O data pins Conditions Min Typ Max Unit VCC = 3.6 V; VI = VCC or GND - 0.1 ±1 µA VCC = 0 V or 3.6 V; VI = 5.5 V - 0.1 10 µA VCC = 3.6 V; VI = VCC [3] - 0.1 1 µA VCC = 3.6 V; VI = 0 V [3] - 0.1 −5 µA IOFF output power-down current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 µA IHOLD bus hold current D inputs VCC = 3.0 V; VI = 0.8 V [5] 75 130 - µA VCC = 3.0 V; VI = 2.0V [5] −75 −140 - µA VCC = 0 V to 3.6 V; VI = 3.6 V [5] ±500 - - µA - 10 125 µA IEX external current into output output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V IPU power-up 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI =VCC or GND; nOE = don’t care [10] - 1 ±100 µA IPD power-down 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI =VCC or GND; nOE = don’t care [10] - 1 ±100 µA IOZ 3-state OFF-state output current VCC = 3.6 V; VI = VIH or VIL output HIGH; VO = 3.0 V - 0.5 5 µA output LOW; VO = 0.5 V - +0.5 −5 µA supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A - 0.04 0.1 mA ICC outputs HIGH-state outputs LOW-state outputs disabled - 3.7 6 mA [7] - 0.04 0.1 mA [8] - 0.04 0.4 mA ∆ICC additional supply current per VCC = 3.0 V to 3.6 V; one input at input pin VCC − 0.6 V; other inputs at VCC or GND Ci input capacitance nCP and nOE VI = 0 V or VCC - 3 - pF Co output capacitance outputs disabled; VO = 0 V or VCC - 9 - pF [1] Typical values are at VCC = 2.5 V and Tamb = 25 °C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at VCC or GND. [4] Not guaranteed [5] This is the bus-hold overdrive current required to force the input to the opposite logic state. [6] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [7] ICC is measured with outputs pulled to VCC or GND. [8] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. [9] Typical values are at VCC = 3.3 V and Tamb = 25 °C. [10] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 9 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 11. Dynamic characteristics Table 8: Dynamic characteristics Tamb = −40 °C to +85 °C; GND = 0 V; for test circuit see Figure 9. Symbol Parameter VCC = 2.5 V ± 0.2 Conditions Min Typ Max Unit V [1] fmax maximum clock frequency see Figure 5 150 - - MHz tPLH propagation delay nCP to nQx see Figure 5 1.5 2.6 4.2 ns tPHL propagation delay nCP to nQx see Figure 5 1.5 2.8 4.5 ns tPZH output enable time to HIGH-level see Figure 6 1.0 3.4 5.6 ns tPZL output enable time to LOW-level see Figure 7 1.0 2.6 4.7 ns tPHZ output disable time from HIGH-level see Figure 6 2.0 2.7 4.4 ns tPLZ output disable time from LOW-level see Figure 7 1.0 2.0 3.3 ns tsu(H) setup time HIGH nDx to nCP see Figure 8 1.0 0 - ns tsu(L) setup time LOW nDx to nCP see Figure 8 1.5 0.4 - ns th(H) hold time HIGH nDx to nCP see Figure 8 0.5 0 - ns th(L) hold time LOW nDx to nCP see Figure 8 0.5 0 - ns tWH nCP pulse width HIGH see Figure 5 1.5 - - ns tWL nCP pulse width LOW see Figure 5 1.5 - - ns VCC = 3.3 V ± 0.3 V [2] fmax maximum clock frequency see Figure 5 250 - - MHz tPLH propagation delay nCP to nQx see Figure 5 1.0 2.1 3.2 ns tPHL propagation delay nCP to nQx see Figure 5 1.0 2.3 3.2 ns tPZH output enable time to HIGH-level see Figure 6 1.0 2.3 3.8 ns tPZL output enable time to LOW-level see Figure 7 1.0 2.0 3.2 ns tPHZ output disable time from HIGH-level see Figure 6 1.0 2.7 4.2 ns tPLZ output disable time from LOW-level see Figure 7 1.0 2.6 3.6 ns tsu(H) setup time HIGH nDx to nCP see Figure 8 1.0 0 - ns tsu(L) setup time LOW nDx to nCP see Figure 8 1.5 0 - ns th(H) hold time HIGH nDx to nCP see Figure 8 0.5 0 - ns th(L) hold time LOW nDx to nCP see Figure 8 0.5 0 - ns tWH nCP pulse width HIGH see Figure 5 1.5 - - ns tWL nCP pulse width LOW see Figure 5 1.5 - - ns [1] Typical values are at VCC = 2.5 V and Tamb = 25 °C. [2] Typical values are at VCC = 3.3 V and Tamb = 25 °C. 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 10 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 12. Waveforms 1/f max VI input nCP VM VM VM 0V t WH t WL t PHL t PLH VOH VM output nQx VM VOL 001aad250 Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 5. Propagation delay clock input to output, clock pulse width and maximum clock frequency VI VM VM input nOE 0V t PZH t PHZ VOH VY VM output nQx 0V 001aad251 Measurement points are given in Table 9. VOH is typical voltage output drop that occur with the output load. Fig 6. 3-state output enable time to HIGH-level and output disable time from HIGH-level VI VM VM input nOE 0V t PZL t PLZ VOH VM output nQx VX VOL 001aad253 Measurement points are given in Table 9. VOL is typical voltage output drop that occur with the output load. Fig 7. 3-state output enable time to LOW-level and output disable time from LOW-level 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 11 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state VI VM input nDx VM VM VM 0V t s(H) t h(H) t s(L) t h(L) VI output nCP VM VM 0V 001aad252 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 8. Data setup and hold times Table 9: Measurement points Supply voltage Input Output VM VM VX VY ≥3V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V ≤ 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH − 0.15 V 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 12 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state tW VI 90 % negative pulse 90 % VM VM 10 % 0V VI tTHL(tf) tTLH(tr) tTLH(tr) tTHL(tf) 90 % positive pulse VM VM 10 % 0V 10 % tW 001aac221 Measurement points are given in Table 9. a. Input pulse definition VEXT VCC PULSE GENERATOR VI RL VO DUT CL RT RL mna616 Test data is given in Table 10. Definitions: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. b. Test circuit Fig 9. Load circuitry for switching times Table 10: Test data Input Load VI fi tW 3.0 V or VCC whichever is less ≤ 10 MHz 500 ns tr, tf ≤ 2.5 ns 50 pF 9397 750 15193 Product data sheet CL VEXT RL tPLH, tPHL tPHZ, tPZH tPLZ, tPZL 500 Ω open GND 6 V or 2 × VCC © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 13 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 13. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 10. Package outline SOT362-1 (TSSOP48) 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 14 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Fig 11. Package outline SOT370-1 (SSOP48) 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 15 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 14. Revision history Table 11: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74ALVT16374_4 20050704 Product data sheet - 9397 750 15193 74ALVT16374_3 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • Section 2 “Features”: Changed JEDEC Std 17 to JESD78 Section 11 “Dynamic characteristics”: Changed tPLZ typical value to 2.6 ns and maximum value to 3.6 ns 74ALVT16374_3 19991018 Product specification - 9397 750 06513 74ALVT16374_2 74ALVT16374_2 19980213 Product specification - 9397 750 03565 74ALVT16374_1 74ALVT16374_1 19960610 Product specification - - - 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 16 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. Trademarks 17. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 9397 750 15193 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 04 — 4 July 2005 17 of 18 74ALVT16374 Philips Semiconductors 16-bit edge-triggered D-type flip-flop; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 4 July 2005 Document number: 9397 750 15193 Published in The Netherlands