74ALVT16821
20-bit bus interface D-type flip-flop; positive-edge trigger;
3-state
Rev. 03 — 13 June 2005
Product data sheet
1. General description
The 74ALVT16821 high-performance Bipolar Complementary Metal Oxide
Semiconductor (BiCMOS) device combines low static and dynamic power dissipation with
high speed and high output drive. It is designed for VCC operation at 2.5 V or 3.3 V with
I/O compatibility to 5 V.
The 74ALVT16821 has two 10-bit, edge triggered registers, with each register coupled to
a 3-state output buffer. The two sections of each register are controlled independently by
the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active low output enable (nOE) controls all ten 3-state buffers independent of the
register operation. When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
2. Features
■
■
■
■
■
■
■
■
■
■
20-bit positive-edge triggered register
5 V I/O compatible
Multiple VCC and GND pins minimize switching noise
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
Output capability: +64 mA and −32 mA
Latch-up protection:
◆ JESD78: exceeds 500 mA
ESD protection:
◆ MIL STD 883, method 3015: exceeds 2000 V
◆ Machine model: exceeds 200 V
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPLH
propagation delay nCP to nQx
CL = 50 pF
-
2.6
-
ns
tPHL
propagation delay nCP to nQx
CL = 50 pF
-
2.7
-
ns
Ci
input capacitance
VI = 0 V or VCC
3
-
pF
Co
output capacitance
VO = 0 V or VCC
9
-
pF
ICC
supply current
outputs disabled
-
40
-
µA
tPLH
propagation delay nCP to nQx
CL = 50 pF
-
1.7
-
ns
tPHL
propagation delay nCP to nQx
CL = 50 pF
-
1.8
-
ns
VCC = 2.5 V
VCC = 3.3 V
Ci
input capacitance
VI = 0 V or VCC
3
-
pF
Co
output capacitance
VO = 0 V or VCC
9
-
pF
ICC
supply current
outputs disabled
70
-
µA
-
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74ALVT16821DL
−40 °C to +85 °C
SSOP56
plastic shrink small outline package; 56 leads;
body width 7.5 mm
SOT371-1
74ALVT16821DGG
−40 °C to +85 °C
TSSOP56
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
SOT364-1
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
2 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
5. Functional diagram
1OE
1CP
1
56
EN2
C1
28
2OE
29
2CP
55
54
52
51
49
48
47
45
44
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
43
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
56
1CP
1
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2
3
5
6
8
9
10
12
13
14
42
41
40
38
37
36
34
33
31
30
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
29
2CP
28
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
EN4
C3
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
1D
2
3D
4
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
001aad155
001aad153
Fig 1. Logic symbol
nD0
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
Fig 2. IEC logic symbol
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
001aad156
Fig 3. Logic diagram
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
3 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
6. Pinning information
6.1 Pinning
1OE
1
56 1CP
1Q0
2
55 1D0
1Q1
3
54 1D1
GND
4
53 GND
1Q2
5
52 1D2
1Q3
6
51 1D3
VCC
7
1Q4
8
50 VCC
49 1D4
1Q5
9
48 1D5
1Q6 10
47 1D6
GND 11
46 GND
1Q7 12
45 1D7
1Q8 13
44 1D8
1Q9 14
43 1D9
16821
2Q0 15
42 2D0
2Q1 16
41 2D1
2Q2 17
40 2D2
GND 18
39 GND
2Q3 19
38 2D3
2Q4 20
37 2D4
2Q5 21
36 2D5
VCC 22
2Q6 23
35 VCC
34 2D6
2Q7 24
33 2D7
GND 25
32 GND
2Q8 26
31 2D8
2Q9 27
30 2D9
2OE 28
29 2CP
001aad154
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Pin description
Symbol
Pin
Description
1OE
1
1 output enable input (active LOW)
1Q0
2
1 data output 0
1Q1
3
1 data output 1
GND
4
ground (0 V)
1Q2
5
1 data output 2
1Q3
6
1 data output 3
VCC
7
supply voltage
1Q4
8
1 data output 4
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
4 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
Table 3:
Pin description …continued
Symbol
Pin
Description
1Q5
9
1 data output 5
1Q6
10
1 data output 6
GND
11
ground (0 V)
1Q7
12
1 data output 7
1Q8
13
1 data output 8
1Q9
14
1 data output 9
2Q0
15
2 data output 0
2Q1
16
2 data output 1
2Q2
17
2 data output 2
GND
18
ground (0 V)
2Q3
19
2 data output 3
2Q4
20
2 data output 4
2Q5
21
2 data output 5
VCC
22
supply voltage
2Q6
23
2 data output 6
2Q7
24
2 data output 7
GND
25
ground (0 V)
2Q8
26
2 data output 8
2Q9
27
2 data output 9
2OE
28
2 output enable input (active LOW)
2CP
29
2 clock pulse input (active rising edge)
2D9
30
2 data input 9
2D8
31
2 data input 8
GND
32
ground (0 V)
2D7
33
2 data input 7
2D6
34
2 data input 6
VCC
35
supply voltage
2D5
36
2 data input 5
2D4
37
2 data input 4
2D3
38
2 data input 3
GND
39
ground (0 V)
2D2
40
2 data input 2
2D1
41
2 data input 1
2D0
42
2 data input 0
1D9
43
1 data input 9
1D8
44
1 data input 8
1D7
45
1 data input 7
GND
46
ground (0 V)
1D6
47
1 data input 6
1D5
48
1 data input 5
1D4
49
1 data input 4
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
5 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
Table 3:
Pin description …continued
Symbol
Pin
Description
VCC
50
supply voltage
1D3
51
1 data input 3
1D2
52
1 data input 2
GND
53
ground (0 V)
1D1
54
1 data input 1
1D0
55
1 data input 0
1CP
56
1 clock pulse input (active rising edge)
7. Functional description
7.1 Function table
Table 4:
Function table
Operating mode
[1]
Input
Internal register
Output
nOE
nCP
nDx
Load and read
register
L
↑
l
L
L
L
↑
h
H
H
Hold
L
NC
X
NC
NC
Disable outputs
H
NC
X
NC
Z
H
↑
Dx
Dx
Z
[1]
nQx
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VCC
supply voltage
Max
Unit
−0.5
+4.6
V
[1]
−1.2
+7.0
V
[1]
−0.5
+7.0
V
VI
input voltage
VO
output voltage
output in OFF-state or
HIGH-state
IIK
input diode current
VI < 0 V
-
−50
mA
IOK
output diode current
VO < 0 V
-
−50
mA
9397 750 15123
Product data sheet
Min
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
6 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
Table 5:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
IO
output current
output in LOW-state
-
128
mA
output in HIGH-state
-
−64
mA
−65
+150
°C
-
150
°C
Tstg
storage temperature
Tj
junction temperature
[2]
[1]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.5 V
VCC
supply voltage
2.3
-
2.7
V
VI
input voltage
0
-
5.5
V
VIH
HIGH-level input voltage
1.7
-
-
V
VIL
LOW-level input voltage
-
-
0.7
V
IOH
HIGH-level output current
-
-
−8
mA
IOL
LOW-level output current
none
-
-
8
mA
current duty cycle
≤ 50 %; f ≥ 1 kHz
-
-
24
mA
∆t/∆V
input transition rise or fall rate
outputs enabled
-
-
10
ns/V
Tamb
ambient temperature
free-air
−40
-
+85
°C
VCC = 3.3V
VCC
supply voltage
3.0
-
3.6
V
VI
input voltage
0
-
5.5
V
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
IOH
HIGH-level output current
IOL
LOW-level output current
-
-
−32
mA
none
-
-
32
mA
current duty cycle
≤ 50 %; f ≥ 1 kHz
-
-
64
mA
∆t/∆V
input transition rise or fall rate
outputs enabled
-
-
10
ns/V
Tamb
ambient temperature
free-air
−40
-
+85
°C
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
7 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb = −40 °C to +85 °C .
Symbol
Parameter
VCC = 2.5 V ± 0.2 V
Conditions
Min
Typ
Max
−0.85 −1.2
Unit
[1]
VIK
input diode voltage
VCC = 2.3 V; IIK = −18 mA
-
VOH
HIGH-level output voltage
VCC = 2.3 V to 3.6 V; IO = −100 µA
VCC − 0.2 VCC
-
V
VCC = 2.3 V; IO = −8 mA
1.8
2.1
-
V
VCC = 2.3 V; IO = 100 µA
-
0.07
0.2
V
VCC = 2.3 V; IO = 24 mA
-
0.3
0.5
V
-
-
0.4
V
-
-
0.55
V
-
0.1
±1
µA
0.1
10
µA
VOL
LOW-level output voltage
VCC = 2.3 V; IO = 8 mA
VRST
power-up LOW-state output VCC = 2.7 V; IO = 1 mA; VI = VCC or GND
voltage
ILI
input leakage current
control pins
I/O data pins
[2]
VCC = 2.7 V; VI = VCC or GND
V
VCC = 0 V or 2.7 V; VI = 5.5 V
[3]
VCC = 2.7 V; VI = VCC
[3]
-
0.1
1
µA
VCC = 2.7 V; VI = 0 V
[3]
-
+0.1
−5
µA
-
0.1
±100 µA
IOFF
power-down leakage
current
VCC = 0 V; VI or VO = 0 V to 4.5 V
IHOLD
data input bus hold current
VCC = 2.3 V; VI = 0.7 V
[4]
-
90
-
µA
VCC = 2.3 V; VI = 1.7 V
[4]
-
−10
-
µA
µA
external current into output
output HIGH-state; VO = 5.5 V; VCC = 2.3 V
IPU
power-up 3-state output
current
IPD
IOZ
IEX
ICC
-
10
125
VCC ≤ 1.2 V; VO = 0.5 V to VCC;
VI = GND or VCC; VOE = don’t care
[5]
-
1
±100 µA
power-down 3-state output
current
VCC ≤ 1.2 V; VO = 0.5 V to VCC;
VI = GND or VCC; VOE = don’t care
[5]
-
1
±100 µA
3-state OFF-state output
current
VCC = 3.6 V; VI = VIL or VIH
output HIGH-state; VO = 3.0 V
-
0.5
5
µA
output LOW-state; VO = 0.5 V
-
+0.5
−5
µA
-
0.04
0.1
mA
-
2.3
4.5
mA
0.04
0.1
mA
-
0.04
0.4
mA
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
outputs LOW-state
outputs disabled
VCC = 2.3 V to 2.7 V; one input at VCC − 0.6 V,
other inputs at VCC or GND
[6]
∆ICC
additional supply current
per input pin
Ci
input capacitance
VI = 0 V or VCC
-
3
-
pF
Co
output capacitance
VO = 0 V or VCC
-
9
-
pF
9397 750 15123
Product data sheet
[7]
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
8 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb = −40 °C to +85 °C .
Symbol
Parameter
VCC = 3.3 V ± 0.3 V
Conditions
Min
Typ
Max
−0.85 −1.2
Unit
[8]
VIK
input diode voltage
VCC = 3.0 V; IIK = −18 mA
-
VOH
HIGH-level output voltage
VCC = 3.0 V to 3.6 V; IO = −100 µA
VCC − 0.2 VCC
-
V
VCC = 3.0 V; IO = −32 mA
2.0
2.3
-
V
IO = 100 µA
-
0.07
0.2
V
IO = 16 mA
-
0.25
0.4
V
IO = 32 mA
-
0.3
0.5
V
-
0.4
0.55
V
-
-
0.55
V
LOW-level output voltage
VOL
VCC = 3.0 V
IO = 64 mA
VRST
power-up LOW-state output VCC = 3.6 V; IO = 1 mA; VI = VCC or GND
voltage
ILI
input leakage current
control pins
I/O data pins
V
[2]
-
0.1
±1
µA
VCC = 0 V or 3.6 V; VI = 5.5 V
[3]
-
0.1
10
µA
VCC = 3.6 V; VI = VCC
[3]
-
0.5
1
µA
VCC = 3.6 V; VI = 0 V
[3]
-
+0.1
−5
µA
-
0.1
±100 µA
VCC = 3.6 V; VI = VCC or GND
IOFF
power-down leakage
current
VCC = 0 V; VI or VO = 0 V to 4.5 V
IHOLD
data input bus hold current
VCC = 3 V; VI = 0.8 V
[4]
75
130
-
µA
VCC = 3 V; VI = 2.0 V
[4]
−75
−140 -
µA
VCC = 0 V to 3.6 V; VCC = 3.6 V
[4]
±500
-
-
µA
µA
IEX
external current into output
output HIGH-state; VO = 5.5 V; VCC = 2.3 V
-
10
125
IPU
power-up 3-state output
current
VCC ≤ 1.2 V; VO = 0.5 V to VCC;
VI = GND or VCC; VOE = don’t care
[9]
-
1
±100 µA
IPD
power-down 3-state output
current
VCC ≤ 1.2 V; VO = 0.5 V to VCC;
VI = GND or VCC; VOE = don’t care
[9]
-
1
±100 µA
IOZ
3-state OFF-state output
current
VCC = 3.6 V; VI = VIL or VIH
output HIGH-state; VO = 3.0 V
-
0.5
5
µA
output LOW-state; VO = 0.5 V
-
+0.5
−5
µA
-
0.07
0.1
mA
supply current
ICC
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH-state
outputs LOW-state
outputs disabled
-
5.1
7
mA
[6]
-
0.07
0.1
mA
[7]
-
0.04
0.4
mA
∆ICC
additional supply current
per input pin
VCC = 3 V to 3.6 V; one input at VCC − 0.6 V,
other inputs at VCC or GND
Ci
input capacitance
VI = 0 V or VCC
-
3
-
pF
Co
output capacitance
VO = 0 V or VCC
-
9
-
pF
[1]
All typical values are measured at VCC = 2.5 V and Tamb = 25 °C.
[2]
For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3]
Unused pins at VCC or GND.
[4]
This is the bus hold overdrive current required to force the input to the opposite logic state.
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
9 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
[5]
This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to (2.5 ± 0.2) V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[6]
ICC is measured with outputs pulled up to VCC or pulled down to ground.
[7]
This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
[8]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
[9]
This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1,2 V to (3.3 ± 0.3) V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
11. Dynamic characteristics
Table 8:
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Tamb = −40 °C to +85 °C.
Symbol
Parameter
VCC = 2.5 V ± 0.2 V
Conditions
Min
Typ
Max
Unit
[1]
tPLH
propagation delay nCP to nQx
see Figure 5
1.0
2.6
4.0
ns
tPHL
propagation delay nCP to nQx
see Figure 5
1.0
2.7
4.4
ns
tPZH
output enable time nOE to nQx
see Figure 7
1.5
2.8
4.6
ns
tPZL
output enable time nOE to nQx
see Figure 8
1.0
1.8
4.1
ns
tPHZ
output disable time nOE to nQx
see Figure 7
1.5
2.7
4.4
ns
tPLZ
output disable time nOE to nQx
see Figure 8
1.0
2.1
3.3
ns
tsu(H)
set-up time HIGH nDx to nCP
see Figure 6
1.5
0.1
-
ns
tsu(L)
set-up time LOW nDx to nCP
see Figure 6
2.0
0.5
-
ns
th(H)
hold time HIGH nDx to nCP
see Figure 6
0.3
−0.5
-
ns
th(L)
hold time LOW nDx to nCP
see Figure 6
0.5
−0.1
tWH
nCP pulse width HIGH
see Figure 5
1.5
-
-
ns
tWL
nCP pulse width LOW
see Figure 5
1.5
-
-
ns
fmax
maximum clock frequency
see Figure 5
150
-
-
MHz
VCC = 3.3 V ± 0.3 V
ns
[2]
tPLH
propagation delay nCP to nQx
see Figure 5
0.5
1.7
3.0
ns
tPHL
propagation delay nCP to nQx
see Figure 5
0.5
1.8
3.2
ns
tPZH
output enable time nOE to nQx
see Figure 7
1.0
2.1
3.5
ns
tPZL
output enable time nOE to nQx
see Figure 8
0.5
1.4
3.0
ns
tPHZ
output disable time nOE to nQx
see Figure 7
1.5
2.9
4.2
ns
tPLZ
output disable time nOE to nQx
see Figure 8
1.5
2.4
3.4
ns
tsu(H)
set-up time HIGH nDx to nCP
see Figure 6
1.5
0.1
-
ns
tsu(L)
set-up time LOW nDx to nCP
see Figure 6
1.5
0.1
-
ns
th(H)
hold time, HIGH nDx to nCP
see Figure 6
0.5
0.1
-
ns
th(L)
hold time, LOW nDx to nCP
see Figure 6
0.5
0.1
-
ns
tWH
nCP pulse width HIGH
see Figure 5
1.5
-
-
ns
tWL
nCP pulse width LOW
see Figure 5
1.5
-
-
ns
fmax
maximum clock frequency
see Figure 5
150
-
-
MHz
[1]
All typical values are measured at VCC = 2.5 V and Tamb = 25 °C.
[2]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
10 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
12. Waveforms
1/fmax
VI
input nCP
VM
0V
tWH
tWL
tPHL
tPLH
VOH
output nQx
VM
VOL
001aad157
Measurement points are given in Table 9.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay clock input (nCP) to output (nQx), clock pulse (nCP) width and
maximum clock frequency
VI
input nCP
VM
GND
tsu(H)
th(H)
tsu(L)
th(L)
VI
input nDx
VM
0V
001aad158
Measurement points are given in Table 9.
VOL and VOH are typical voltage output drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 6. Data set-up and hold times
VI
VM
input nOE
GND
t PZH
t PHZ
VOH
output nQx
VM
VY
VOL
001aad159
Measurement points are given in Table 9.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. 3-state output enable time to HIGH-level and output disable time from HIGH-level
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
11 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
VI
VM
input nOE
GND
tPZL
tPLZ
VOH
VM
output nQx
VX
VOL
001aad161
Measurement points are given in Table 9.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 8. 3-state output enable time to LOW-level and output disable time from LOW-level
Table 9:
Measurement points
Supply voltage
Input
Output
VM
VM
VY
≥3V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
≤ 2.7 V
0.5 × VCC
0.5 × VCC
VOL + 0.15 V
VOH − 0.15 V
9397 750 15123
Product data sheet
VX
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
12 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
tW
VI
90 %
negative
pulse
90 %
VM
VM
10 %
0V
VI
tTHL(tf)
tTLH(tr)
tTLH(tr)
tTHL(tf)
90 %
positive
pulse
VM
VM
10 %
0V
10 %
tW
001aac221
Measurement points are given in Table 9.
a. Input pulse definition
VEXT
VCC
PULSE
GENERATOR
VI
RL
VO
DUT
CL
RT
RL
mna616
Test data is given in Table 10.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
b. Test circuit
Fig 9. Load circuitry for switching times
Table 10:
Test data
Input
Load
VI
fi
tW
tr, tf
CL
RL
3.0 V or VCC
whichever is
less
≤ 10 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω 6 V or
2 × VCC
9397 750 15123
Product data sheet
VEXT
tPLZ, tPZL tPLH, tPHL tPHZ, tPZH
open
GND
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
13 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
13. Package outline
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
D
E
A
X
c
y
HE
v M A
Z
29
56
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
28
1
bp
e
0
detail X
w M
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
18.55
18.30
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8
o
0
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT371-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-118
Fig 10. Package outline SOT371-1 (SSOP56)
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
14 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
28
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 11. Package outline SOT364-1 (TSSOP56)
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
15 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
14. Revision history
Table 11:
Revision history
Document ID
Release date
Data sheet status
Change notice
Doc. number
Supersedes
74ALVT16821_3
20050613
Product data sheet
-
9397 750 15123
74ALVT16821_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
•
•
Section 2: modified ‘JEDEC Std 17’ into ‘JESD78’.
Table 8: changed maximum values of propagation delay, output enable time and output disable
time.
74ALVT16821_2
19980213
Product specification
9397 750 03574
74ALVT16821_1
74ALVT16821_1
19970501
Product specification
-
-
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
16 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
15. Data sheet status
Level
Data sheet status [1]
Product status [2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Trademarks
17. Disclaimers
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 15123
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 13 June 2005
17 of 18
74ALVT16821
Philips Semiconductors
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
20. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
17
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 6
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information . . . . . . . . . . . . . . . . . . . . 17
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 13 June 2005
Document number: 9397 750 15123
Published in The Netherlands
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