74AUP1G04GW

74AUP1G04 Low-power inverter Rev. 03 — 5 November 2009 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114F Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78B Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74AUP1G04 Low-power inverter 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G04GV 74AUP1G04GW 74AUP1G04GM 74AUP1G04GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SC-74A TSSOP5 XSON6 XSON6 Description plastic surface-mounted package; 5 leads plastic thin shrink small outline package; 5 leads; body width 1.25 mm Version SOT753 SOT353-1 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code[1] p04 pC pC pC Type number 74AUP1G04GV 74AUP1G04GW 74AUP1G04GM 74AUP1G04GF [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 2 A Y 4 2 1 4 A Y mna110 mna108 mna109 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 2 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter 6. Pinning information 6.1 Pinning 74AUP1G04 74AUP1G04 n.c. A 1 2 GND GND 3 001aaf022 n.c. 5 VCC 1 6 VCC n.c. A 74AUP1G04 1 2 3 6 5 4 VCC n.c. Y A 2 5 n.c. 3 4 Y GND 4 Y 001aaf023 001aaf024 Transparent top view Transparent top view Fig 4. Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 6.2 Pin description Table 3. Symbol n.c. A GND Y n.c. VCC Pin description Pin SOT353-1/SOT753 SOT886/SOT891 1 2 3 4 5 1 2 3 4 5 6 not connected data input A ground (0 V) data output Y not connected supply voltage Description 7. Functional description Table 4. Input A L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output Y H L 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 3 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 −50 [1] [1] Max +4.6 +4.6 VCC + 0.5 +4.6 ±20 +50 +150 250 Unit V mA V mA V V mA mA mA °C mW VO < 0 V active mode power-down mode VO = 0 V to VCC −0.5 −0.5 −50 −65 Tamb = −40 °C to +125 °C [2] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 4 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 0.8 V to 3.6 V active mode power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 −40 0 Max 3.6 3.6 VCC 3.6 +125 200 Unit V V V V °C ns/V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VIH HIGH-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V 74AUP1G04_3 Conditions Min Typ Max - Unit V V V V 0.70 × VCC 0.65 × VCC 1.6 2.0 VCC − 0.1 1.11 1.32 2.05 1.9 2.72 2.6 - 0.30 × VCC V 0.35 × VCC V 0.7 0.9 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 V V V V V V V V V V V V V V V V V V 0.75 × VCC - © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 5 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II IOFF ∆IOFF ICC ∆ICC CI CO VIH input leakage current power-off leakage current additional power-off leakage current supply current additional supply current input capacitance output capacitance HIGH-state input voltage Conditions VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF input leakage current power-off leakage current additional power-off leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V 0.1 0.3 × VCC 0.37 0.35 0.33 0.45 0.33 0.45 ±0.5 ±0.5 ±0.6 V V V V V V V V µA µA µA VCC − 0.1 0.7 × VCC 1.03 1.30 1.97 1.85 2.67 2.55 V V V V V V V V Min Typ 0.8 1.7 Max ±0.1 ±0.2 ±0.2 0.5 40 Unit µA µA µA µA µA pF pF V V V V Tamb = −40 °C to +85 °C 0.70 × VCC 0.65 × VCC 1.6 2.0 - 0.30 × VCC V 0.35 × VCC V 0.7 0.9 V V 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 6 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC ∆ICC supply current additional supply current Conditions VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC input leakage current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V 0.11 0.41 0.39 0.36 0.50 0.36 0.50 ±0.75 ±0.75 ±0.75 1.4 75 V V V V V V V µA µA µA µA µA 0.33 × VCC V VCC − 0.11 0.6 × VCC 0.93 1.17 1.77 1.67 2.40 2.30 V V V V V V V V Min Typ Max 0.9 50 Unit µA µA Tamb = −40 °C to +125 °C VIH HIGH-state input voltage 0.75 × VCC 0.70 × VCC 1.6 2.0 V V V V 0.25 × VCC V 0.30 × VCC V 0.7 0.9 V V 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 7 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol tPHL, tPLH Parameter HIGH-to-LOW and LOW-to-HIGH propagation delay A to Y Conditions see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A to Y see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A to Y see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A to Y see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 4.4 3.6 3.2 2.9 2.9 33.6 8.9 6.3 5.3 4.5 4.2 16.0 10.8 9.0 6.5 5.4 ns ns ns ns ns ns 3.2 2.6 2.3 2.1 2.0 23.3 6.7 4.7 4.0 3.3 3.1 13.0 8.6 6.7 5.1 4.2 ns ns ns ns ns ns 2.8 2.3 2.0 1.7 1.6 19.8 5.9 4.2 3.5 2.9 2.7 12.2 7.5 5.9 4.6 3.8 ns ns ns ns ns ns 2.4 1.8 1.5 1.2 1.1 16.0 5.0 3.6 2.9 2.4 2.1 10.3 6.4 5.0 3.9 3.2 ns ns ns ns ns ns Min Typ [1] Max Unit Tamb = 25 °C; CL = 5 pF 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 8 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol CPD Parameter Conditions [2] Min Typ [1] Max Unit Tamb = 25 °C power dissipation capacitance f = 1 MHz; VI = GND to VCC VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] All typical values are measured at nominal VCC. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. - 2.5 2.7 2.8 3.0 3.5 4.0 - pF pF pF pF pF pF Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol CL = 5 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A to Y see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A to Y see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 2.6 2.1 1.8 1.5 1.4 13.7 8.7 7.0 5.4 4.5 2.6 2.1 1.8 1.5 1.4 15.1 9.6 7.7 6.0 5.0 ns ns ns ns ns 2.1 1.6 1.4 1.1 1.0 11.4 7.4 5.9 4.5 3.9 2.1 1.6 1.4 1.1 1.0 12.6 8.2 6.5 5.0 4.3 ns ns ns ns ns Parameter Conditions −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 9 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A to Y see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A to Y see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 4.0 3.2 2.9 2.6 2.6 19.0 12.9 10.5 7.6 6.2 4.0 3.2 2.9 2.6 2.6 20.9 14.2 11.6 8.4 6.9 ns ns ns ns ns 3.0 2.4 2.1 1.8 1.8 15.8 10.0 8.0 6.1 5.0 3.0 2.4 2.1 1.8 1.8 17.4 11.0 8.8 6.8 5.5 ns ns ns ns ns Parameter Conditions −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 12. Waveforms VI A input GND t PHL VOH Y output VOL VM mna640 VM t PLH Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The data input (A) to output (Y) propagation delays Table 10. VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 × VCC Input VM 0.5 × VCC VI VCC tr = tf ≤ 3.0 ns Supply voltage 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 10 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter VCC VEXT 5 kΩ G VI VO DUT RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to the output impedance Zo of the pulse generator VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times Table 11. VCC 0.8 V to 3.6 V [1] Test data Load CL 5 pF, 10 pF, 15 pF and 30 pF RL [1] Supply voltage VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ 2 × VCC 5 kΩ or 1 MΩ For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 11 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E A X c y HE vMA Z 5 4 A2 A1 (A3) θ A 1 e e1 bp 3 wM detail X Lp L 0 1.5 scale 3 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 θ 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 9. Package outline SOT353-1 (TSSOP5) 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 12 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter Plastic surface-mounted package; 5 leads SOT753 D B E A X y HE vMA 5 4 Q A A1 c 1 2 3 detail X Lp e bp wM B 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT753 REFERENCES IEC JEDEC JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 10. Package outline SOT753 (SC-74A) 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 13 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 11. Package outline SOT886 (XSON6) 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 14 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 12. Package outline SOT891 (XSON6) 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 15 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter 14. Abbreviations Table 12. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 13. Revision history Release date 20091105 Data sheet status Product data sheet Change notice Supersedes 74AUP1G04_2 Document ID 74AUP1G04_3 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74AUP1G04GV (SC-74A) package. Product data sheet Product data sheet 74AUP1G04_1 - 74AUP1G04_2 74AUP1G04_1 20060628 20050718 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 16 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP1G04_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 5 November 2009 17 of 18 NXP Semiconductors 74AUP1G04 Low-power inverter 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 November 2009 Document identifier: 74AUP1G04_3