74AUP1G08GW/S470125

74AXP1G08 Low-power 2-input AND gate Rev. 1 — 15 January 2014 Product data sheet 1. General description The 74AXP1G08 is a single 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits               Wide supply voltage range from 0.7 V to 2.75 V Low input capacitance; CI = 0.5 pF (typical) Low output capacitance; CO = 1.0 pF (typical) Low dynamic power consumption; CPD = 2.4 pF at VCC = 1.2 V (typical) Low static power consumption; ICC = 0.6 A (85 C maximum) High noise immunity Complies with JEDEC standard:  JESD8-12A.01 (1.1 V to 1.3 V)  JESD8-11A.01 (1.4 V to 1.6 V)  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A.01 (2.3 V to 2.7 V) ESD protection:  HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV  CDM JESD22-C101E exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 2.75 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C 74AXP1G08 NXP Semiconductors Low-power 2-input AND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G08GM 40 C to +85 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.5 mm 74AUP1G08GN 40 C to +85 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74AUP1G08GS 40 C to +85 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 74AUP1G08GX 40 C to +85 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8  0.8  0.35 mm SOT1226 4. Marking Table 2. Marking Type number Marking code[1] 74AUP1G08GM rE 74AUP1G08GN rE 74AUP1G08GS rE 74AUP1G08GX rE [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram $ 1 B 2 A 1 Y 4 Logic symbol 74AXP1G08 Product data sheet 4 < 2 mna113 Fig 1. & mna114 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 January 2014 % PQD Fig 3. Logic diagram © NXP B.V. 2014. All rights reserved. 2 of 17 74AXP1G08 NXP Semiconductors Low-power 2-input AND gate 6. Pinning information 6.1 Pinning $;3* $;3* %   9&& % $   QF *1'   <  9&&  <  *1' $  DDD DDD 7UDQVSDUHQWWRSYLHZ 7UDQVSDUHQWWRSYLHZ Fig 4.  Pin configuration SOT886, SOT1115 and SOT1202 (XSON6) Fig 5. Pin configuration SOT1226 (X2SON5) 6.2 Pin description Table 3. Pin description Symbol Pin Description X2SON5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 7. Functional description Table 4. Function table[1] Input Output A B Y L L L L H L H L L H H H [1] H = HIGH voltage level; L = LOW voltage level. 74AXP1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 January 2014 © NXP B.V. 2014. All rights reserved. 3 of 17 74AXP1G08 NXP Semiconductors Low-power 2-input AND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO < 0 V [1] Min Max Unit 0.5 +3.3 V 50 - mA 0.5 +3.3 V 50 - mA 0.5 +3.3 V VO output voltage IO output current - 20 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 250 mW [1] VO = 0 V to VCC Tamb = 40 C to +85 C The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC Conditions Min Max Unit supply voltage 0.7 2.75 V VI input voltage 0 2.75 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 2.75 V 40 +85 C 0 200 ns/V Tamb ambient temperature t/V input transition rise and fall rate 74AXP1G08 Product data sheet VCC = 0.7 V to 2.75 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 January 2014 © NXP B.V. 2014. All rights reserved. 4 of 17 74AXP1G08 NXP Semiconductors Low-power 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions, unless otherwise specified; voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL Tamb = 40 C to +85 C Conditions Unit Min Typ 25 C Max 25 C Max 85 C VCC = 0.75 V to 0.85 V 0.75VCC - - - V VCC = 1.1 V to 1.95 V 0.65VCC - - - V VCC = 2.3 V to 2.7 V 1.6 - - - V VCC = 0.75 V to 0.85 V - - 0.25VCC 0.25VCC V VCC = 1.1 V to 1.95 V - - 0.35VCC 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 0.7 V IO = 20 A; VCC = 0.7 V - 0.69 - - V IO = 100 A; VCC = 0.75 V 0.65 - - - V IO = 2 mA; VCC = 1.1 V 0.825 - - - V IO = 3 mA; VCC = 1.4 V 1.05 - - - V IO = 4.5 mA; VCC = 1.65 V 1.2 - - - V IO = 8 mA; VCC = 2.3 V 1.7 - - - V IO = 20 A; VCC = 0.7 V - 0.01 - - V IO = 100 A; VCC = 0.75 V - - 0.1 0.1 V IO = 2 mA; VCC = 1.1 V - - 0.275 0.275 V IO = 3 mA; VCC = 1.4 V - - 0.35 0.35 V IO = 4.5 mA; VCC = 1.65 V - - 0.45 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.7 0.7 V - 0.001 0.1 0.5 A II input leakage current VI = 0 V to 2.75 V; VCC = 0 V to 2.75 V [1] IOFF power-off leakage current VI or VO = 0 V to 2.75 V; VCC = 0 V [1] - 0.01 0.1 0.5 A IOFF additional power-off leakage current VI or VO = 0 V or 2.75 V; VCC = 0 V to 0.1 V [1] - 0.02 0.1 0.5 A ICC supply current VI = 0 V or VCC; IO = 0 A [1] - 0.01 0.3 0.6 A ICC additional supply VI = VCC  0.5 V; IO = 0 A; current VCC = 2.5 V - 2 100 150 A [1] All typical values are measured at VCC = 1.2 V. 74AXP1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 January 2014 © NXP B.V. 2014. All rights reserved. 5 of 17 74AXP1G08 NXP Semiconductors Low-power 2-input AND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 12. Symbol Parameter propagation delay tpd Tamb = 25 C Conditions Tamb = 40 C to +85 C Unit Min Typ[1] Max Min Max 3 11 37 2 122 ns VCC = 1.1 V to 1.3 V 2.0 4.3 6.9 1.8 7.3 ns VCC = 1.4 V to 1.6 V 1.6 3.2 4.7 1.5 5.0 ns A, B to Y; see Figure 6 [2][3] VCC = 0.75 V to 0.85 V VCC = 1.65 V to 1.95 V 1.3 2.6 3.8 1.2 4.1 ns VCC = 2.3 V to 2.7 V 1.1 2.0 2.8 0.9 3.0 ns - - - 1.0 - ns VCC = 2.7 V; see Figure 6 [4] tt transition time CI input capacitance VI = 0 V or VCC; VCC = 0 V to 2.75 V - 0.5 - - - pF CO output capacitance - 1.0 - - - pF CPD power dissipation fi = 1 MHz; VI = 0 V to VCC capacitance VCC = 0.75 V to 0.85 V VO = 0 V; VCC = 0 V [5] - 2.3 - - - pF VCC = 1.1 V to 1.3 V - 2.4 - - - pF VCC = 1.4 V to 1.6 V - 2.4 - - - pF VCC = 1.65 V to 1.95 V - 2.5 - - - pF VCC = 2.3 V to 2.7 V - 2.8 - - - pF [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] For additional propagation delay values at different load capacitances see Figure 7 to Figure 11. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + CL  VCC2  fo where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching. 74AXP1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 January 2014 © NXP B.V. 2014. All rights reserved. 6 of 17 74AXP1G08 NXP Semiconductors Low-power 2-input AND gate 12. Waveforms 9, $%LQSXW 90 90 *1' W3+/ 92+ W3/+