74AUP1G57

74AUP1G57 Low-power configurable multiple function gate Rev. 03 — 22 June 2009 Product data sheet 1. General description The 74AUP1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G57 has Schmitt trigger inputs making it capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I ESD protection: N HBM JESD22-A114E exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G57GW 74AUP1G57GM 74AUP1G57GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SC-88 XSON6 XSON6 Description plastic surface-mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code[1] aC aC aC Type number 74AUP1G57GW 74AUP1G57GM 74AUP1G57GF [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 3 4 B 1 Y A C 6 001aab583 Fig 1. Logic symbol 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 2 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 6. Pinning information 6.1 Pinning 74AUP1G57 74AUP1G57 B GND 1 2 6 5 C VCC A A 3 001aab591 B 1 6 C B GND 74AUP1G57 1 2 3 6 5 4 C VCC Y GND 2 5 VCC 3 4 001aab592 Y A 4 Y 001aae058 Transparent top view Transparent top view Fig 2. Pin configuration SOT363 (SC-88) Fig 3. Pin configuration SOT886 (XSON6) Fig 4. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Symbol B GND A Y VCC C Pin description Pin 1 2 3 4 5 6 Description data input ground (0 V) data input data output supply voltage data input 7. Functional description Table 4. Input C L L L L H H H H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output B L L H H L L H H A L H L H L H L H Y H L H L L L H H 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 3 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 7.1 Logic configurations Table 5. Function selection table Figure see Figure 5 see Figure 8 see Figure 6 and Figure 7 see Figure 6 and Figure 7 see Figure 8 see Figure 5 see Figure 9 see Figure 10 see Figure 11 Logic function 2-input AND 2-input AND with both inputs inverted 2-input NAND with inverted input 2-input OR with inverted input 2-input NOR 2-input NOR with both inputs inverted 2-input XNOR Inverter Buffer VCC B C Y B 1 2 B C Y 3 6 5 4 Y B C Y C B C Y B 1 2 3 6 5 4 Y C VCC 001aab584 001aab585 Fig 5. 2-input AND gate or 2-input NOR gate with both inputs inverted Fig 6. 2-input NAND gate with input B inverted or 2-input OR gate with inverted C input VCC VCC A C Y 1 2 A C Y A 3 6 5 4 Y A C Y A C A C Y 1 2 3 6 5 4 Y C 001aab586 001aab587 Fig 7. 2-input NAND gate with input C inverted or 2-input OR gate with inverted A input Fig 8. 2-input NOR gate or 2-input AND gate with both inputs inverted VCC VCC B B C Y 1 2 3 6 5 4 Y A Y A 001aab588 001aab589 C 1 2 3 6 5 4 Y Fig 9. 2-input XNOR gate Fig 10. Inverter 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 4 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate VCC B B Y 1 2 3 6 5 4 Y 001aab590 Fig 11. Buffer 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 −50 [1] Max +4.6 +4.6 +4.6 ±20 50 +150 250 Unit V mA V mA V mA mA mA °C mW VO < 0 V Active mode and Power-down mode VO = 0 V to VCC −0.5 −50 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 7. Symbol VCC VI VO Tamb Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature Active mode Power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 −40 Max 3.6 3.6 VCC 3.6 +125 Unit V V V V °C 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 5 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VOH HIGH-level output voltage VI = VT+ or VT− IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VT+ or VT− IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC CI CO VOH input leakage current power-off leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V 1.1 1.7 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 ±0.1 ±0.2 ±0.2 0.5 40 V V V V V V V V µA µA µA µA µA pF pF VCC − 0.1 1.11 1.32 2.05 1.9 2.72 2.6 V V V V V V V V 0.75 × VCC Conditions Min Typ Max Unit additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V supply current additional supply current input capacitance output capacitance HIGH-level output voltage VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VI = GND or VCC; VCC = 0 V to 3.6 V VO = GND; VCC = 0 V VI = VT+ or VT− IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V Tamb = −40 °C to +85 °C VCC − 0.1 0.7 × VCC 1.03 1.30 1.97 1.85 2.67 2.55 V V V V V V V V 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 6 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage Conditions VI = VT+ or VT− IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC input leakage current power-off leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V 0.1 0.3 × VCC 0.37 0.35 0.33 0.45 0.33 0.45 ±0.5 ±0.5 ±0.6 0.9 50 V V V V V V V V µA µA µA µA µA Min Typ Max Unit additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V supply current additional supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VI = VT+ or VT− IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V Tamb = −40 °C to +125 °C VOH HIGH-level output voltage VCC − 0.11 0.6 × VCC 0.93 1.17 1.77 1.67 2.40 2.30 0.11 0.41 0.39 0.36 0.50 0.36 0.50 ±0.75 ±0.75 V V V V V V V V V V V V V V V µA µA VOL LOW-level output voltage VI = VT+ or VT− IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V 0.33 × VCC V II IOFF input leakage current power-off leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 7 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ∆IOFF ICC ∆ICC Conditions Min Typ Max ±0.75 1.4 75 Unit µA µA µA additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V supply current additional supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13. Symbol Parameter Conditions Min CL = 5 pF tpd propagation delay A, B and C to Y; see Figure 12 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tpd propagation delay A, B and C to Y; see Figure 12 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 15 pF tpd propagation delay A, B and C to Y; see Figure 12 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [2] [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit 2.8 2.2 2.1 2.0 1.8 22.6 6.5 4.6 3.9 3.1 2.8 12.6 7.6 6.2 4.5 3.9 2.5 2.5 2.0 1.8 1.5 13.0 8.2 6.8 5.1 4.1 13.2 8.6 7.2 5.3 4.3 ns ns ns ns ns ns 3.2 2.6 2.5 2.4 2.3 26.1 7.3 5.2 4.5 3.7 3.4 14.4 8.7 7.0 5.2 4.6 2.8 2.8 2.2 2.1 1.9 14.9 9.3 7.8 5.9 4.9 15.2 9.8 8.2 6.2 5.1 ns ns ns ns ns ns 3.4 2.8 2.6 2.6 2.5 31.6 8.0 5.7 4.9 4.1 3.8 15.7 9.4 7.7 5.7 5.0 3.1 3.1 2.5 2.4 2.2 16.7 10.4 8.7 6.5 5.5 17.0 10.9 9.2 6.9 5.7 ns ns ns ns ns ns 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 8 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13. Symbol Parameter Conditions Min CL = 30 pF tpd propagation delay A, B and C to Y; see Figure 12 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 5 pF, 10 pF, 15 pF and 30 pF CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] [3] [4] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL. All specified values are the average typical values over all stated loads. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [3][4] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit 4.6 3.6 3.5 3.4 3.2 37.8 10.4 7.4 6.2 5.2 4.9 20.9 12.2 9.9 7.4 6.6 3.9 3.8 3.1 3.1 2.8 21.8 13.4 11.1 8.3 7.0 22.3 14.1 11.8 8.8 7.4 ns ns ns ns ns ns - 2.6 2.8 2.9 3.1 3.7 4.3 - - - - pF pF pF pF pF pF 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 9 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 12. Waveforms VI A, B, C input GND t PHL VOH Y output VOL t PLH VOH Y output VOL VM VM t PHL VM VM t PLH VM VM 001aab593 Measurement points are given in Table 10. VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. Input A, B and C to output Y propagation delay times Table 10. VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 × VCC Input VM 0.5 × VCC VI VCC tr = tf ≤ 3.0 ns Supply voltage 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 10 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate VCC VEXT 5 kΩ G VI VO DUT RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Load circuitry for switching times Table 11. VCC 0.8 V to 3.6 V [1] Test data Load CL RL [1] Supply voltage VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ 2 × VCC 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ For measuring enable and disable times, RL = 5 kΩ. For measuring propagation delays, set-up and hold times, and pulse width, RL = 1 MΩ. 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 11 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 13. Transfer characteristics Table 12. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter Conditions Min VT+ positive-going threshold voltage see Figure 14 and Figure 15 VCC = 0.8 V VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VT− negative-going threshold voltage see Figure 14 and Figure 15 VCC = 0.8 V VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VH hysteresis voltage (VT+ − VT−); see Figure 14, Figure 15, Figure 16 and Figure 17 VCC = 0.8 V VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V 0.07 0.08 0.18 0.27 0.53 0.79 0.50 0.46 0.56 0.66 0.92 1.31 0.07 0.08 0.18 0.27 0.53 0.79 0.50 0.46 0.56 0.66 0.92 1.31 0.50 0.46 0.56 0.66 0.92 1.31 V V V V V V 0.10 0.26 0.39 0.47 0.69 0.88 0.60 0.65 0.75 0.84 1.04 1.24 0.10 0.26 0.39 0.47 0.69 0.88 0.60 0.65 0.75 0.84 1.04 1.24 0.60 0.65 0.75 0.84 1.04 1.24 V V V V V V 0.30 0.53 0.74 0.91 1.37 1.88 0.60 0.90 1.11 1.29 1.77 2.29 0.30 0.53 0.74 0.91 1.37 1.88 0.60 0.90 1.11 1.29 1.77 2.29 0.62 0.92 1.13 1.31 1.80 2.32 V V V V V V 25 °C Typ Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit 14. Waveform transfer characteristics VO VT+ VI VT− VH VO VH VT− VT+ VI mna207 mna208 VT+ and VT− limits at 70 % and 20 %. Fig 14. Transfer characteristic 74AUP1G57_3 Fig 15. Definition of VT+, VT−, and VH © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 12 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 240 ICC (µA) 160 001aad691 80 0 0 0.4 0.8 1.2 1.6 VI (V) 2.0 Fig 16. Typical transfer characteristics; VCC = 1.8 V 1200 ICC (µA) 800 001aad692 400 0 0 1.0 2.0 VI (V) 3.0 Fig 17. Typical transfer characteristics; VCC = 3.0 V 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 13 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 15. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 18. Package outline SOT363 (SC-88) 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 14 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 19. Package outline SOT886 (XSON6) 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 15 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 20. Package outline SOT891 (XSON6) 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 16 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 16. Abbreviations Table 13. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 17. Revision history Table 14. Revision history Release date 20090622 Data sheet status Product data sheet Product data sheet Product data sheet Change notice Supersedes 74AUP1G57_2 74AUP1G57_1 Document ID 74AUP1G57_3 Modifications: 74AUP1G57_2 74AUP1G57_1 • Table 6: Derating factor XSON6 packages has been changed. 20090323 20061123 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 17 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 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Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP1G57_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 22 June 2009 18 of 19 NXP Semiconductors 74AUP1G57 Low-power configurable multiple function gate 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Transfer characteristics. . . . . . . . . . . . . . . . . . 12 Waveform transfer characteristics . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 June 2009 Document identifier: 74AUP1G57_3