74AUP2G08GM

74AUP2G08 Low-power dual 2-input AND gate Rev. 03 — 29 May 2008 Product data sheet 1. General description The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1 000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD78 Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP2G08DC 74AUP2G08GT 74AUP2G08GD 74AUP2G08GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C VSSOP8 XSON8 XSON8U XQFN8U Description Version plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm SOT902-1 Type number 4. Marking Table 2. Marking codes Marking code p08 p08 p08 p08 Type number 74AUP2G08DC 74AUP2G08GT 74AUP2G08GD 74AUP2G08GM 5. Functional diagram & 1A 1B 2A 2B 1Y A 2Y & B 001aah789 Y 001aah788 mna221 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 2 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 6. Pinning information 6.1 Pinning 74AUP2G08 1A 1 8 VCC 1B 2 7 1Y 74AUP2G08 2Y 1A 1B 2Y GND 1 2 3 4 001aae236 3 6 2B 8 7 6 5 VCC 1Y 2B 2A GND 4 5 2A 001aae237 Transparent top view Fig 4. Pin configuration SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT833-1 (XSON8) 74AUP2G08 terminal 1 index area 1Y 1 VCC 8 74AUP2G08 1A 1B 2Y GND 1 2 3 4 8 7 6 5 VCC 7 1A 2B 1Y 2B 2A 2A 2 6 1B 3 4 5 2Y GND 001aae357 001aai215 Transparent top view Transparent top view Fig 6. Pin configuration SOT996-2 (XSON8U) Fig 7. Pin configuration SOT902-1 (XQFN8U) 6.2 Pin description Table 3. Symbol Pin description Pin SOT765-1, SOT833-1 and SOT996-2 1A, 2A 1B, 2B GND 1Y, 2Y VCC 74AUP2G08_3 Description SOT902-1 7, 3 6, 2 4 1, 5 8 data input data input ground (0 V) data output supply voltage © NXP B.V. 2008. All rights reserved. 1, 5 2, 6 4 7, 3 8 Product data sheet Rev. 03 — 29 May 2008 3 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 7. Functional description Table 4. Input nA L L H H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output nB L H L H nY L L L H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −0.5 [1] Max +4.6 −50 +4.6 −50 +4.6 ±20 +50 −50 +150 250 Unit V mA V mA V mA mA mA °C mW VO < 0 V Active mode and Power-down mode VO = 0 V to VCC −0.5 −65 Tamb = −40 °C to +125 °C [2] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For VSSOP8 packages: above 110 °C the value of Ptot derates linearly at 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly at 2.4 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb ∆t/∆V Operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 0.8 V to 3.6 V Active mode Power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 −40 Max 3.6 3.6 VCC 3.6 +125 200 Unit V V V V °C ns/V 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 4 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC CI CO input leakage current power-off leakage current additional power-off leakage current supply current additional supply current input capacitance output capacitance VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V [1] Conditions Min Typ Max - Unit V V V V 0.70 × VCC 0.65 × VCC 1.6 2.0 VCC − 0.1 1.11 1.32 2.05 1.9 2.72 2.6 0.6 1.3 0.30 × VCC V 0.35 × VCC V 0.7 0.9 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 ±0.1 ±0.2 ±0.2 0.5 40 V V V V V V V V V V V V V V V V V V µA µA µA µA µA pF pF 0.75 × VCC - 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 5 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC input leakage current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V [1] Conditions Min Typ Max - Unit V V V V 0.70 × VCC 0.65 × VCC 1.6 2.0 VCC − 0.1 0.7 × VCC 1.03 1.30 1.97 1.85 2.67 2.55 - 0.30 × VCC V 0.35 × VCC V 0.7 0.9 0.1 0.3 × VCC 0.37 0.35 0.33 0.45 0.33 0.45 ±0.5 ±0.5 ±0.6 0.9 50 V V V V V V V V V V V V V V V V V V µA µA µA µA µA 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 6 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC input leakage current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V [1] Conditions Min Typ Max - Unit V V V V 0.75 × VCC 0.70 × VCC 1.6 2.0 - 0.25 × VCC V 0.30 × VCC V 0.7 0.9 0.11 0.41 0.39 0.36 0.50 0.36 0.50 ±0.75 ±0.75 ±0.75 1.4 75 V V V V V V V V V V V V V V V V V µA µA µA µA µA VCC − 0.11 0.6 × VCC 0.93 1.17 1.77 1.67 2.40 2.30 - 0.33 × VCC V [1] One input at VCC − 0.6 V, other input at VCC or GND. 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 7 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions Tamb = 25 °C Min CL = 5 pF tpd propagation delay nA or nB to nY; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tpd propagation delay nA or nB to nY; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 15 pF tpd propagation delay nA or nB to nY; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 30 pF tpd propagation delay nA or nB to nY; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [2] [2] [2] [2] Tamb = −40 °C to +125 °C Unit Min Max (85 °C) Max (125 °C) Typ[1] Max 2.6 1.6 1.3 1.1 1.0 17.0 5.1 3.7 3.0 2.4 2.2 10.8 6.5 5.2 4.0 3.5 2.1 1.5 1.3 1.0 0.9 11.7 7.5 6.1 4.8 4.3 12.9 8.3 6.7 5.3 4.8 ns ns ns ns ns ns 2.4 2.0 1.7 1.4 1.3 20.6 6.0 4.3 3.6 2.9 2.7 12.5 7.6 6.1 4.8 4.2 2.2 1.8 1.6 1.3 1.2 13.6 8.9 7.2 5.7 4.7 15.0 9.8 7.9 6.3 5.2 ns ns ns ns ns ns 3.4 2.3 1.9 1.7 1.5 24.1 6.8 4.9 4.0 3.4 3.1 14.2 8.6 6.9 5.5 4.8 3.1 2.1 1.8 1.6 1.5 15.7 10.1 8.2 6.5 5.9 17.3 11.2 9.0 7.2 6.5 ns ns ns ns ns ns 4.6 3.4 2.6 2.3 2.2 34.4 9.1 6.4 5.3 4.5 4.2 19.4 11.5 9.1 7.2 6.2 4.1 2.9 2.4 2.2 2.1 21.8 13.6 10.9 8.6 7.5 24.0 15.0 12.1 9.5 8.3 ns ns ns ns ns ns 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 8 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions Tamb = 25 °C Min CL = 5 pF, 10 pF, 15 pF and 30 pF CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] [3] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [3] Tamb = −40 °C to +125 °C Unit Min Max (85 °C) Max (125 °C) Typ[1] Max - 2.5 2.6 2.7 2.8 3.2 3.7 - - - - pF pF pF pF pF pF 12. Waveforms VI nA, nB input GND t PHL VOH nY output VOL VM mna224 VM t PLH Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 9. VCC The data input (nA or nB) to output (nY) propagation delays Measurement points Output VM 0.5 × VCC Input VM 0.5 × VCC VI VCC tr = tf ≤ 3.0 ns Supply voltage 0.8 V to 3.6 V 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 9 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate VCC VEXT 5 kΩ G VI VO DUT RT CL RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 10. VCC Load circuit for measuring switching times Test data Load CL 5 pF, 10 pF, 15 pF and 30 pF RL [1] Supply voltage 0.8 V to 3.6 V [1] VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ 2 × VCC 5 kΩ or 1 MΩ For measuring enable and disable times, RL = 5 kΩ. For measuring propagation delays, set-up and hold times and pulse width, RL = 1 MΩ. 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 10 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 13. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 10. Package outline SOT765-1 (VSSOP8) 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 11 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 11. Package outline SOT833-1 (XSON8) 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 12 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 12. Package outline SOT996-2 (XSON8U) 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 13 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 13. Package outline SOT902-1 (XQFN8U) 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 14 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 14. Abbreviations Table 11. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 12. Revision history Release date 20080529 Data sheet status Product data sheet Product data sheet Product data sheet Change notice Supersedes 74AUP2G08_2 74AUP2G08_1 Document ID 74AUP2G08_3 Modifications: 74AUP2G08_2 74AUP2G08_1 • Added type number 74AUP2G08GD (XSON8U package) 20080407 20061006 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 15 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP2G08_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 29 May 2008 16 of 17 NXP Semiconductors 74AUP2G08 Low-power dual 2-input AND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 May 2008 Document identifier: 74AUP2G08_3