74AUP2G38DC

74AUP2G38 Low-power dual 2-input NAND gate; open drain Rev. 04 — 8 October 2009 Product data sheet 1. General description The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114F Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101D exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD78B Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP2G38DC 74AUP2G38GT 74AUP2G38GD 74AUP2G38GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C VSSOP8 XSON8 XSON8U XQFN8U Description Version plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm SOT902-1 Type number 4. Marking Table 2. Marking codes Marking code[1] a38 a38 a38 a38 Type number 74AUP2G38DC 74AUP2G38GT 74AUP2G38GD 74AUP2G38GM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram & 1A 1B 2A 2B 1Y A 2Y Y & B GND 001aah753 001aah754 mnb131 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 2 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 6. Pinning information 6.1 Pinning 74AUP2G38 1A 1 8 VCC 1B 2 7 1Y 74AUP2G38 2Y 1A 1B 2Y GND 1 2 3 4 001aaf547 3 6 2B 8 7 6 5 VCC 1Y 2B 2A GND 4 5 2A 001aaf548 Transparent top view Fig 4. Pin configuration SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT833-1 (XSON8) 74AUP2G38 terminal 1 index area 1Y 1 VCC 8 74AUP2G38 1A 1B 2Y GND 1 2 3 4 8 7 6 5 VCC 7 1A 2B 1Y 2B 2A 2A 2 6 1B 3 4 5 2Y GND 001aaf034 001aak747 Transparent top view Transparent top view Fig 6. Pin configuration SOT996-2 (XSON8U) Fig 7. Pin configuration SOT902-1 (XQFN8U) 6.2 Pin description Table 3. Symbol Pin description Pin SOT765-1, SOT833-1 and SOT996-2 1A, 2A 1B, 2B GND 1Y, 2Y VCC 74AUP2G38_4 Description SOT902-1 7, 3 6, 2 4 1, 5 8 data input data input ground (0 V) data output supply voltage © NXP B.V. 2009. All rights reserved. 1, 5 2, 6 4 7, 3 8 Product data sheet Rev. 04 — 8 October 2009 3 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 7. Functional description Table 4. Input nA L L H H [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state. Function table[1] Output nB L H L H nY Z Z Z L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 −50 [1] Max +4.6 +4.6 +4.6 +20 +50 +150 250 Unit V mA V mA V mA mA mA °C mW VO < 0 V Active mode and Power-down mode VO = 0 V to VCC −0.5 −50 −65 Tamb = −40 °C to +125 °C [2] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For VSSOP8 packages: above 110 °C the value of Ptot derates linearly at 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb ∆t/∆V Operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 0.8 V to 3.6 V Active mode and Power-down mode Conditions Min 0.8 0 0 −40 0 Max 3.6 3.6 3.6 +125 200 Unit V V V °C ns/V 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 4 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOZ IOFF ∆IOFF ICC ∆ICC CI CO input leakage current OFF-state output current power-off leakage current additional power-off leakage current supply current additional supply current input capacitance output capacitance VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI = VIH or VIL; VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V 0.7 0.9 0.1 0.3VCC 0.31 0.31 0.31 0.44 0.31 0.44 ±0.1 ±0.1 ±0.2 ±0.2 0.5 40 V V V V V V V V µA µA µA µA µA µA pF pF 0.70VCC 0.65VCC 1.6 2.0 0.30VCC 0.35VCC 0.7 0.9 V V V V V V V V Conditions Min Typ Max Unit 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 5 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOZ IOFF ∆IOFF ICC ∆ICC input leakage current OFF-state output current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI = VIH or VIL; VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V 0.1 0.3VCC 0.37 0.35 0.33 0.45 0.33 0.45 ±0.5 ±0.5 ±0.5 ±0.6 0.9 50 V V V V V V V V µA µA µA µA µA µA 0.70VCC 0.65VCC 1.6 2.0 0.30VCC 0.35VCC 0.7 0.9 V V V V V V V V Conditions Min Typ Max Unit 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 6 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOZ IOFF ∆IOFF ICC ∆ICC input leakage current OFF-state output current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI = VIH or VIL; VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V 0.11 0.33VCC 0.41 0.39 0.36 0.50 0.36 0.50 ±0.75 ±0.75 ±0.75 ±0.75 1.4 75 V V V V V V V V µA µA µA µA µA µA 0.75VCC 0.70VCC 1.6 2.0 0.25VCC 0.30VCC 0.7 0.9 V V V V V V V V Conditions Min Typ Max Unit 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 7 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions 25 °C Min CL = 5 pF tpd propagation delay nA, nB to nY; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tpd propagation delay nA, nB to nY; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 15 pF tpd propagation delay nA, nB to nY; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 30 pF tpd propagation delay nA, nB to nY; see Figure 8 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [2] [2] [2] [2] −40 °C to +125 °C Typ[1] Max Min Max (85 °C) Max (125 °C) Unit 1.9 1.5 1.2 1.0 0.9 13.5 4.6 3.3 2.9 2.2 2.3 10.4 6.5 5.1 3.8 4.0 1.8 1.4 1.1 0.9 0.8 11.4 7.4 5.9 4.5 4.5 12.6 8.2 6.5 4.9 4.9 ns ns ns ns ns ns 2.3 1.8 1.6 1.4 1.3 16.3 5.6 4.1 3.8 2.9 3.2 12.3 7.6 6.1 4.6 5.7 2.1 1.7 1.4 1.2 1.1 13.7 8.8 7.1 5.4 6.4 15.1 9.7 7.8 5.9 7.0 ns ns ns ns ns ns 2.6 2.1 1.9 1.6 1.6 19.0 6.6 4.8 4.6 3.6 4.1 14.2 8.7 7.6 5.6 7.5 2.4 1.9 1.7 1.5 1.4 15.8 10.1 8.5 6.3 8.3 17.4 11.1 9.3 6.9 9.1 ns ns ns ns ns ns 3.6 2.9 2.6 2.4 2.3 27.0 9.5 7.0 7.0 5.4 6.5 19.5 11.5 12.1 8.9 12.7 3.2 2.6 2.3 2.1 2.1 21.8 13.6 13.3 9.9 13.9 24.0 15.0 14.6 10.9 15.3 ns ns ns ns ns ns 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 8 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions 25 °C Min CL = 5 pF, 10 pF, 15 pF and 30 pF CPD power dissipation capacitance f = 1 MHz; VI = GND to VCC VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] [3] All typical values are measured at nominal VCC. tpd is the same as tPZL and tPLZ. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N where: fi = input frequency in MHz; VCC = supply voltage in V; N = number of inputs switching. [3] −40 °C to +125 °C Typ[1] Max Min Max (85 °C) Max (125 °C) Unit - 0.6 0.7 0.8 0.9 1.1 1.4 - - - - pF pF pF pF pF pF 12. Waveforms VI nA, nB input GND t PLZ VCC nY output VOL VX mnb132 VM t PZL VM Measurement points are given in Table 9. Logic level VOL is a typical output voltage level that occurs with the output load. Fig 8. Table 9. VCC The data input (nA, nB) to output (nY) propagation delays Measurement points Input VM 0.5VCC 0.5VCC 0.5VCC Output VM 0.5VCC 0.5VCC 0.5VCC VX VOL + 0.1 V VOL + 0.15 V VOL + 0.3 V Supply voltage 0.8 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 9 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain VCC VEXT 5 kΩ G VI VO DUT RT CL RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 10. VCC Load circuitry for switching times Test data Load CL RL[1] 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ 2VCC Supply voltage 0.8 V to 3.6 V [1] For measuring enable and disable times RL = 5 kΩ. For measuring propagation delays, set-up times, hold times and pulse width, RL = 1 MΩ. 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 10 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 13. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 10. Package outline SOT765-1 (VSSOP8) 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 11 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 11. Package outline SOT833-1 (XSON8) 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 12 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 12. Package outline SOT996-2 (XSON8U) 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 13 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 13. Package outline SOT902-1 (XQFN8U) 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 14 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 14. Abbreviations Table 11. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 12. Revision history Release date 20091008 Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet Change notice Supersedes 74AUP2G38_3 74AUP2G38_2 74AUP2G38_1 Document ID 74AUP2G38_4 Modifications: 74AUP2G38_3 74AUP2G38_2 74AUP2G38_1 • Added type number 74AUP2G38GD (XSON8U / SOT996-2) package. 20090616 20080312 20061016 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 15 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 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Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP2G38_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 8 October 2009 16 of 17 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate; open drain 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 October 2009 Document identifier: 74AUP2G38_4