74AUP2GU04

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NXP(恩智浦)
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描述：
74AUP2GU04 - Low-power dual unbuffered inverter - NXP Semiconductors

数据手册：

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数据手册
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74AUP2GU04 数据手册

74AUP2GU04 Low-power dual unbuffered inverter Rev. 02 — 3 July 2009 Product data sheet 1. General description The 74AUP2GU04 provides two unbuffered inverting gates. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I ESD protection: N HBM JESD22-A114E Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages up to 3.6 V I Multiple package options I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP2GU04GW 74AUP2GU04GM 74AUP2GU04GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SC-88 XSON6 XSON6 Description plastic surface-mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 4. Marking Table 2. Marking Marking code[1] aD aD aD Type number 74AUP2GU04GW 74AUP2GU04GM 74AUP2GU04GF [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 6 1 1 6 540 Ω VCC 50 Ω A 3 2A 2Y 4 3 1 4 Y mnb106 mnb107 001aad073 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74AUP2GU04 74AUP2GU04 1A GND 1 2 6 5 1Y GND VCC 2A 2A 3 001aad699 1A 1 6 1Y 1A GND 74AUP2GU04 1 2 3 6 5 4 1Y VCC 2Y 2 5 VCC 3 4 2Y 2A 4 2Y 001aad700 001aad701 Transparent top view Transparent top view Fig 4. Pin conﬁguration SOT363 (SC-88) Fig 5. Pin conﬁguration SOT886 (XSON6) Fig 6. Pin conﬁguration SOT891 (XSON6) 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 2 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 6.2 Pin description Table 3. Symbol 1A GND 2A 2Y VCC 1Y Pin description Pin 1 2 3 4 5 6 Description data input ground (0 V) data input data output supply voltage data output 7. Functional description Table 4. Input nA L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output nY H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 −50 [2] Max +4.6 +4.6 VCC + 0.5 ±20 50 +150 250 Unit V mA V mA V mA mA mA °C mW VO < 0 V VO = 0 V to VCC −0.5 −50 −65 Tamb = −40 °C to +125 °C [3] - The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 3 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 0.8 V to 3.6 V Conditions Min 0.8 0 0 −40 0 Max 3.6 3.6 VCC +125 200 Unit V V V °C ns/V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 0.8 V to 3.6 V VCC = 0.8 V to 3.6 V VI = GND or VCC IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = GND or VCC IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II ICC CI CO input leakage current supply current input capacitance output capacitance VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V 1.5 1.8 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 ±0.1 0.5 V V V V V V V V µA µA pF pF VCC − 0.1 1.11 1.32 2.05 1.9 2.72 2.6 V V V V V V V V 0.75 × VCC 0.75 × VCC V 0.25 × VCC V Conditions Min Typ Max Unit 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 4 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 0.8 V to 3.6 V VCC = 0.8 V to 3.6 V VI = GND or VCC IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = GND or VCC IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II ICC input leakage current supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VCC = 0.8 V to 3.6 V VCC = 0.8 V to 3.6 V VI = GND or VCC IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VCC − 0.11 0.6 × VCC 0.93 1.17 1.77 1.67 2.40 2.30 V V V V V V V V 0.1 0.3 × VCC 0.37 0.35 0.33 0.45 0.33 0.45 ±0.5 0.9 V V V V V V V V µA µA VCC − 0.1 0.7 × VCC 1.03 1.30 1.97 1.85 2.67 2.55 V V V V V V V V 0.75 × VCC V 0.25 × VCC V Conditions Min Typ Max Unit Tamb = −40 °C to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 0.75 × VCC V 0.25 × VCC V 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 5 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage Conditions VI = GND or VCC IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II ICC input leakage current supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V 0.11 0.41 0.39 0.36 0.50 0.36 0.50 ±0.75 1.4 V V V V V V V µA µA 0.33 × VCC V Min Typ Max Unit 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min CL = 5 pF tpd propagation delay nA to nY; see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tpd propagation delay nA to nY; see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max Max (85 °C) (125 °C) Unit 0.9 0.7 0.5 0.4 0.3 6.2 2.3 1.7 1.4 1.1 1.0 4.4 3.1 2.6 2.0 1.8 0.9 0.6 0.5 0.4 0.3 4.8 3.4 2.9 2.3 2.1 5.3 3.8 3.2 2.6 2.4 ns ns ns ns ns ns 1.2 1.0 0.8 0.6 0.5 9.6 3.1 2.3 1.9 1.5 1.3 6.1 4.0 3.3 2.7 2.4 1.2 0.9 0.7 0.6 0.5 6.8 4.6 3.8 3.1 2.7 7.5 5.1 4.2 3.5 3.0 ns ns ns ns ns ns 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 6 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min CL = 15 pF tpd propagation delay nA to nY; see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 30 pF tpd propagation delay nA to nY; see Figure 7 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 5 pF, 10 pF, 15 pF and 30 pF CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] [3] [4] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL. All speciﬁed values are the average typical values over all stated loads. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [3][4] [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max Max (85 °C) (125 °C) Unit 1.6 1.3 1.0 0.8 0.7 13.0 3.8 2.8 2.3 1.9 1.6 7.9 4.9 4.0 3.2 2.9 1.4 1.1 0.9 0.8 0.7 8.8 5.7 4.7 3.7 3.3 9.7 6.3 5.2 4.1 3.7 ns ns ns ns ns ns 2.4 2.0 1.7 1.4 1.2 23.2 6.0 4.2 3.6 2.9 2.5 13.1 7.6 6.1 4.8 4.3 2.2 1.8 1.5 1.3 1.1 14.8 9.0 7.2 5.7 5.1 16.3 9.9 8.0 6.3 5.7 ns ns ns ns ns ns - 1.1 1.1 1.3 1.5 3.0 4.5 - - - - pF pF pF pF pF pF 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 7 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 12. Waveforms VI nA input GND t PHL VOH nY output VOL VM VM mna344 VM VM t PLH Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. The data input (nA) to output (nY) propagation delays Table 9. VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 × VCC Input VM 0.5 × VCC VI VCC tr = tf ≤ 3.0 ns Supply voltage VCC VEXT 5 kΩ G VI VO DUT RT CL RL 001aac521 Test data is given in Table 10. Deﬁnitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times Table 10. VCC 0.8 V to 3.6 V [1] Test data Load CL RL [1] Supply voltage VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ 2 × VCC 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, set-up and hold times and pulse width RL = 1 MΩ. 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 8 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 13. Additional characteristics Rbias = 560 kΩ VCC 0.47 µF input output 100 µF VI (f = 1 kHz) A IO GND mna050 ∆I O g fs = --------∆V I VO is constant. Fig 9. Test set-up for measuring forward transconductance 30 gfs (mA/V) 20 001aad074 10 0 0 1 2 3 VCC (V) 4 Tamb = 25 °C. Fig 10. Typical forward transconductance as a function of supply voltage 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 9 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 14. Application information Some applications for the 74AUP2GU04 are: • Linear ampliﬁer (see Figure 11) • Crystal oscillator (see Figure 12) Remark: All values given are typical values unless otherwise speciﬁed. R2 VCC 1 µF R1 U04 ZL mna052 ZL > 10 kΩ. R1 ≥ 3 kΩ. R2 ≤ 1 MΩ. Open loop ampliﬁcation: AOL = 20. Voltage ampliﬁcation: A V = – ----------------------------------------- . A OL R1 1 + ------ ( 1 + A OL ) R2 Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC. Unity gain bandwidth product is 5 MHz. Fig 11. Linear ampliﬁer application R1 R2 U04 C1 C2 out mna053 C1 = 47 pF. C2 = 22 pF. R1 = 1 MΩ to 10 MΩ. R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC = 2 mA at VCC = 3.3 V and f = 10 MHz). Fig 12. Crystal oscillator application 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 10 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 15. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 13. Package outline SOT363 (SC-88) 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 11 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 14. Package outline SOT886 (XSON6) 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 12 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 15. Package outline SOT891 (XSON6) 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 13 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 16. Abbreviations Table 11. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 17. Revision history Table 12. Revision history Release date 20090703 Data sheet status Product data sheet Change notice Supersedes 74AUP2GU04_1 Document ID 74AUP2GU04_2 Modiﬁcations: • • • Section 8 “Limiting values”: Changed: Derating factor XSON6 packages. Section 10 “Static characteristics”: Changed: conditions for HIGH-level output voltage and LOW-level output voltage. Section 11 “Dynamic characteristics”: Changed: typical power dissipation capacitance. Product data sheet - 74AUP2GU04_1 20061215 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 14 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualiﬁcation Production Deﬁnition This document contains data from the objective speciﬁcation for product development. This document contains data from the preliminary speciﬁcation. This document contains the product speciﬁcation. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Deﬁnitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Deﬁnitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values — Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 15 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Additional characteristics . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 July 2009 Document identifier: 74AUP2GU04_2

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