INTEGRATED CIRCUITS
74AVC16836A
20-bit registered driver with inverted
register enable and
Dynamic Controlled Outputs (3-State)
Product data
Supersedes data of 2000 Aug 03
2002 Aug 02
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
FEATURES
74AVC16836A
PIN CONFIGURATION
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7.
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
• Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
• Power off disables 74AVC16836A outputs, permitting Live
Insertion
• Integrated input diodes to minimize input overshoot and
undershoot
• Full PC133 solution provided when used with PCK2509S or
PCK2510S and CBT16292
DESCRIPTION
The 74AVC16836A is a 20-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 8 for typical curves.
CP
OE
1
56
Y0
2
55
A0
Y1
3
54
A1
GND
4
53
GND
Y2
5
52
A2
Y3
6
51
A3
VCC
7
50
VCC
Y4
8
49
A4
Y5
9
48
A5
Y6
10
47
A6
GND
11
46
GND
Y7
12
45
A7
Y8
13
44
A8
Y9
14
43
A9
Y10
15
42
A10
Y11
16
41
A11
Y12
17
40
A12
GND
18
39
GND
Y13
19
38
A13
Y14
20
37
A14
Y15
21
36
A15
VCC
22
35
VCC
Y16
23
34
A16
Y17
24
33
A17
GND
25
32
GND
Y18
26
31
A18
Y19
27
30
A19
NC
28
29
LE
SH00159
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns; CL = 30 pF.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
An to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
tPHL/tPLH
Propagation delay
LE to Yn;
CP to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
CI
Input capacitance
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
TYPICAL
UNIT
2.4
1.7
1.5
ns
2.7
2.1
1.7
ns
3.8
pF
Outputs enabled
25
Output disabled
6
pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
TEMPERATURE
RANGE
ORDER CODE
DRAWING
NUMBER
56-Pin Plastic 0.5 mm pitch TSSOP
–40 to +85 °C
74AVC16836ADGG
SOT364-1
56-Pin Plastic 0.4 mm pitch TVSOP
–40 to +85 °C
74AVC16836ADGV
SOT481-2
PACKAGES
2002 Aug 02
2
853-2211 28696
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
PIN DESCRIPTION
LOGIC SYMBOL (IEEE/IEC)
PIN NUMBER
SYMBOL
28
NC
NAME AND FUNCTION
No connection
2, 3, 5, 6, 8, 9, 10, 12,
13, 14, 15, 16, 17, 19,
20, 21, 23, 24, 26, 27
Y0 to Y19
4, 11, 18, 25, 32, 35, 39,
46, 53
GND
Ground (0V)
7, 22, 35, 50
VCC
1
29
56
Data outputs
OE
1
CP
56
LE
29
EN1
2C3
C3
G2
Y0
2
55
Positive supply voltage
Y1
3
54
Output enable input
(active LOW)
5
52
OE
Y2
Y3
6
Latch enable input
(active LOW)
8
49
LE
Y4
Y5
9
48
Clock input
Y6
10
47
Y7
12
45
Y8
13
44
Y9
14
43
Y10
15
42
Y11
16
41
Y12
17
40
Y13
19
38
Y14
20
37
Y15
21
36
Y16
23
34
Y17
24
33
26
31
27
30
CP
55, 54, 52, 51, 49, 48,
47, 45, 44, 43, 42, 41,
40, 38, 37, 36, 34, 33,
31, 30
74AVC16836A
A0 to A19
Data inputs
LOGIC SYMBOL
OE
Y18
CP
Y19
1∇
1
51
3D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
SH00160
FUNCTION TABLE
LE
INPUTS
D
A1
Y1
LE
CP
TO THE 17 OTHER CHANNELS
H
L
X
Z
↑
SH00201
TYPICAL INPUT (DATA OR CONTROL)
LE
CP
A
H
X
X
X
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
L
H
H
X
Y01
L
H
L
X
Y02
=
=
=
=
=
Z
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
VCC
A1
SH00200
2002 Aug 02
OUTPUTS
OE
3
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
74AVC16836A
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
168-pin SDR SDRAM DIMM
SDRAM
BACK SIDE
FRONT SIDE
AVC16836A
AVC16836A
AVC16836A
PCK2509S or PCK2510S
The PLL clock distribution device and AVC registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00409
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
VI
VO
Tamb
tr, tf
PARAMETER
CONDITIONS
MIN
MAX
UNIT
DC supply voltage (according to JEDEC Low Voltage Standards)
1.65
2.3
3.0
1.95
2.7
3.6
V
DC supply voltage (for low voltage applications)
1.2
3.6
V
DC Input voltage range
0
3.6
V
DC output voltage range; output 3-State
0
3.6
DC output voltage range; output HIGH or LOW state
0
VCC
Operating free-air temperature range
Input rise and fall times
–40
+85
VCC = 1.65 to 2.3 V
0
30
VCC = 2.3 to 3.0 V
0
20
VCC = 3.0 to 3.6 V
0
10
V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
PARAMETER
SYMBOL
VCC
CONDITIONS
DC supply voltage
RATING
UNIT
–0.5 to +4.6
V
IIK
DC input diode current
VI t0
VI
DC input voltage
For all inputs1
IOK
DC output diode current
VO uVCC or VO t 0
VO
DC output voltage; output 3-State
Note 1
VO
DC output voltage; output HIGH or LOW state
Note 1
–0.5 to VCC +0.5
V
IO
DC output source or sink current
VO = 0 to VCC
"50
mA
"100
mA
–65 to +150
°C
IGND, ICC
Tstg
PTOT
DC VCC or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125 °C
above +55°C derate linearly with 8 mW/K
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Aug 02
4
–50
mA
–0.5 to 4.6
V
"50
mA
–0.5 to 4.6
V
600
mW
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
74AVC16836A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
VCC = 1.2 V
VIH
VIL
VOH
VOL
II
IOFF
IOZ
O
ICC
HIGH level Input voltage
MAX
VCC
–
–
0.65VCC
0.9
–
VCC = 2.3 to 2.7 V
1.7
1.2
–
VCC = 3.0 to 3.6 V
VCC = 1.65 to 1.95 V
2.0
1.5
–
VCC = 1.2 V
–
–
GND
VCC = 1.65 to 1.95 V
–
0.9
0.35VCC
VCC = 2.3 to 2.7 V
–
1.2
0.7
VCC = 3.0 to 3.6 V
–
1.5
0.8
VCC = 1.65 to 3.6 V; VI = VIH or VIL;
IO = –100 µA
0 20
VCC0.20
VCC
–
VCC = 1.65 V; VI = VIH or VIL; IO = –4 mA
VCC0.45
VCC0.10
–
VCC = 2.3 V; VI = VIH or VIL; IO = –8 mA
VCC0.55
VCC0.28
–
VCC = 3.0 V; VI = VIH or VIL; IO = –12 mA
VCC0.70
VCC0.32
–
VCC = 1.65 to 3.6 V; VI = VIH or VIL;
IO = 100 µA
–
GND
0 20
0.20
VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA
–
0.10
0.45
VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA
–
0.26
0.55
VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA
–
0.36
0.70
Input
In
ut leakage current
VCC = 3
3.6
6 V;
VI = VCC or GND
–
0.1
2.5
3-State output OFF-state current
VCC = 0 V; VI or VO = 3.6 V
–
0.1
10
VCC = 1.65 to 2.7 V; VI = VIH or VIL;
VO = VCC or GND
–
0.1
5
VCC = 3.0 to 3.6 V; VI = VIH or VIL;
VO = VCC or GND
–
0.1
10
VCC = 1.65 to 2.7 V; VI = VCC or GND; IO = 0
–
0.1
20
VCC = 3.0 to 3.6 V; VI = VCC or GND; IO = 0
–
0.2
40
LOW level Input voltage
HIGH level output voltage
g
LOW level output voltage
g
3 State output OFF-state
OFF state current
3-State
Quiescent supply current
NOTE:
1. All typical values are at Tamb = 25 °C.
2002 Aug 02
UNIT
TYP1
5
V
V
V
V
µA
µA
µA
µA
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
74AVC16836A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC =
1.5 ± 0.1 V
VCC =
1.2 V
VCC = 3.3 ± 0.3 V
VCC = 2.5 ± 0.2 V
VCC = 1.8 ± 0.15 V
MIN
TYP1
MAX
MIN
TYP1
MAX
MIN
TYP1
MAX
MIN
MAX
TYP
UNIT
Propagation
delay
An to Yn
1, 7
0.7
1.5
2.7
0.8
1.7
3.2
1.0
2.4
4.4
2.0
5.3
4.7
ns
Propagation
delay
LE to Yn
2, 7
0.7
1.7
3.4
1.0
2.1
3.5
1.5
2.7
5.0
2.0
5.6
5.0
ns
Propagation
delay
CP to Yn
3, 7
0.7
1.6
3.0
0.8
1.7
3.2
1.2
2.3
4.1
2.0
4.7
5.7
ns
tPZH/tPZL
3-State output
enable time
OE to Yn
6, 7
1.0
1.9
3.6
1.0
2.4
4.0
1.5
3.0
5.4
2.5
6.8
6.0
ns
tPHZ/tPLZ
3-State output
disable time
OE to Yn
6, 7
1.0
2.5
4.8
1.0
2.1
4.7
1.5
3.7
7.5
2.5
7.6
6.6
ns
CP pulse width
HIGH or LOW
3, 7
1.0
–
–
1.2
–
–
2.0
–
–
–
–
–
ns
LE pulse width
HIGH
2, 7
1.0
–
–
1.2
–
–
2.0
–
–
–
–
–
ns
Set-up time
An to CP
5, 7
0.2
0
–
0.3
0
–
0.2
0
–
0.3
–
0
ns
Set-up time
An to LE
4, 7
0.3
0
–
0.6
0.2
–
0.9
0.4
–
1.3
–
1.2
ns
Hold time
An to CP
5, 7
1.2
0.5
–
0.6
0.2
–
0.6
0.2
–
0.6
–
0.1
ns
Hold time
An to LE
4, 7
1.0
0.5
–
0.5
0.1
–
0.4
0
–
0.2
–
–0.7
ns
Maximum clock
pulse frequency
3, 7
500
–
–
400
–
–
250
–
–
–
–
–
MHz
tPHL/tPLH
tW
tSU
S
th
fmax
NOTE:
1. All typical values are measured at Tamb = 25°C and at VCC = 1.8 V, 2.5 V, 3.3 V.
2002 Aug 02
6
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
74AVC16836A
ÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉÉ
ÉÉÉ
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE
VI
VM = 0.5 VCC
VX = VOL + 0.300 V
VY = VOH – 0.300 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
An
INPUT
VM
GND
th
th
tSU
tSU
VI
LE
INPUT
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND
VCC < 2.3 V RANGE
VM
GND
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00166
VM = 0.5 VCC
VX = VOL + 0.15 V
VY = VOH – 0.15 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
Waveform 4. Data set-up and hold times for the An input to
the LE input
VI
VI
VM
CP INPUT
An
INPUT
VM
GND
GND
tsu
tsu
tPLH
tPHL
VI
Yn
OUTPUT
An INPUT
VM
GND
VOL
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
th
th
VOH
VOH
SH00132
VM
Yn OUTPUT
Waveform 1. Input (An) to output (Yn) propagation delay
VOL
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00136
VI
LE INPUT
VM
VM
Waveform 5. Data set-up and hold times for the An input to
the clock CP input
tW
GND
tPHL
tPLH
VOH
VI
VM
Yn OUTPUT
VOL
nOE INPUT
VM
NOTE: VM = 0.5 VCC at VCC = 2.3 to 2.7 V
SH00165
GND
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
tPLZ
tPZL
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
1/fMAX
VI
CP INPUT
GND
VOL
VM
VM
tPHZ
VOH
tPLH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
VOH
VM
VY
VM
GND
outputs
enabled
VOL
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
outputs
disabled
outputs
enabled
SH00135
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
2002 Aug 02
tPZH
tW
tPHL
Yn OUTPUT
VM
VX
SH00137
Waveform 6. 3-State enable and disable times
7
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
TEST CIRCUIT
74AVC16836A
GRAPHS
S1
3.5
RL
VO
VI
PULSE
GENERATOR
2 * VCC
Open
GND
VOL OUTPUT VOLTAGE (V)
VCC
D.U.T.
RT
RL
CL
Test Circuit for switching times
3
2.5
VCC = 3.3 V
2
1.5
VCC = 2.5 V
1
VCC = 1.8 V
0.5
0
0
DEFINITIONS
50
100
150
200
250
I OL OUTPUT CURRENT (mA)
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
SH00204
SWITCH POSITION
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
VCC
GND
VCC
VI
RL
< 2.3 V
VCC
1000 Ω
2.3–2.7 V
VCC
500 Ω
3.0 V
VCC
500 Ω
Figure 1. Output voltage (VOL) vs. output current (IOL)
3.5
VOH OUTPUT VOLTAGE (V)
SV01018
Waveform 7. Load circuitry for switching times
3.0
2.5
2.0
1.5
1.0
V
= 3.3 V
0.5 CC
0.0
–250
VCC = 2.5 V
–200
–150
VCC = 1.8 V
–100
–50
0
I OH OUTPUT CURRENT (mA)
SH00205
Figure 2. Output voltage (VOH) vs. output current (IOH)
A Dynamic Controlled Output (DCO) circuit is designed in. During
the transition, it initially lowers the output impedance to effectively
drive the load and, subsequently, raises the impedance to reduce
noise. Figures 1 and 2 show VOL vs. IOL and VOH vs. IOH curves to
illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DCO circuit provides a
maximum dynamic drive that is equivalent to a high drive standard
output device.
2002 Aug 02
8
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
2002 Aug 02
9
74AVC16836A
SOT364-1
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 4.4 mm
2002 Aug 02
10
74AVC16836A
SOT481-2
Philips Semiconductors
Product data
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs (3-State)
74AVC16836A
Data sheet status
Data sheet status [1]
Product
status [2]
Definitions
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 08-02
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
2002 Aug 02
11
9397 750 10178
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