74AVC16T245

74AVC16T245 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 3 — 9 June 2011 Product data sheet 1. General description The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn are in the high-impedance OFF-state. 2. Features and benefits  Wide supply voltage range:  VCC(A): 0.8 V to 3.6 V  VCC(B): 0.8 V to 3.6 V  Complies with JEDEC standards:  JESD8-12 (0.8 V to 1.3 V)  JESD8-11 (0.9 V to 1.65 V)  JESD8-7 (1.2 V to 1.95 V)  JESD8-5 (1.8 V to 2.7 V)  JESD8-B (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F Class 3B exceeds 8000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101D exceeds 1000 V  Maximum data rates:  380 Mbit/s ( 1.8 V to 3.3 V translation)  200 Mbit/s ( 1.1 V to 3.3 V translation)  200 Mbit/s ( 1.1 V to 2.5 V translation)  200 Mbit/s ( 1.1 V to 1.8 V translation)  150 Mbit/s ( 1.1 V to 1.5 V translation) NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state        100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AVC16T245DGG 74AVC16T245DGV 74AVC16T245EV 74AVC16T245BX 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C TSSOP48 Description Version plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm Type number TSSOP48[1] plastic thin shrink small outline package; 48 leads; SOT480-1 body width 4.4 mm; lead pitch 0.4 mm VFBGA56 plastic very thin fine-pitch ball grid array package; SOT702-1 56 balls; body 4.5  7  0.65 mm HXQFN60U plastic thermal enhanced extremely thin quad flat SOT1134-1 package; no leads; 60 terminals; UTLP based; body 4  6  0.5 mm [1] Also known as TVSOP48. 4. Functional diagram 1DIR 1OE 2DIR 2OE 1A1 1B1 VCC(A) VCC(B) 2A1 2B1 VCC(A) VCC(B) 001aak426 to other seven channels to other seven channels Fig 1. Logic diagram 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 2 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 1B1 VCC(A) VCC(B) 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1OE 1DIR 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2B1 VCC(A) VCC(B) 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2OE 2DIR 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 001aak425 Fig 2. Logic symbol 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 3 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 5. Pinning information 5.1 Pinning 74AVC16T245 1DIR 1B1 1B2 GND 1B3 1B4 VCC(B) 1B5 1B6 1 2 3 4 5 6 7 8 9 48 1OE 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC(A) 41 1A5 40 1A6 39 GND 38 1A7 37 1A8 36 2A1 35 2A2 34 GND 33 2A3 32 2A4 31 VCC(A) 30 2A5 29 2A6 28 GND 27 2A7 26 2A8 25 2OE 001aak427 GND 10 1B7 11 1B8 12 2B1 13 2B2 14 GND 15 2B3 16 2B4 17 VCC(B) 18 2B5 19 2B6 20 GND 21 2B7 22 2B8 23 2DIR 24 ball A1 74AVC16T245 index area 123456 A B C D E F G H J K 001aak428 Transparent top view Fig 3. Pin configuration SOT362-1 and SOT480-1 (TSSOP48) Fig 4. Pin configuration SOT702-1 (VFBGA56) 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 4 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state terminal 1 index area D1 A32 A31 A30 A29 A28 A27 D4 A1 D5 B20 B19 B18 D8 A26 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 GND(1) B11 B12 B13 B15 B16 B17 A25 A24 A23 A22 74AVC16T245 B14 A21 A20 A19 A18 A10 D6 B8 B9 B10 D7 A17 D2 A11 A12 A13 A14 A15 A16 D3 001aak429 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SOT1134-1 (HXQFN60U) 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 5 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 5.2 Pin description Table 2. Symbol Pin description Pin SOT362-1 and SOT480-1 1DIR, 2DIR 1B1 to 1B8 2B1 to 2B8 GND[1] VCC(B) 1OE, 2OE 1A1 to 1A8 2A1 to 2A8 VCC(A) n.c. 1, 24 2, 3, 5, 6, 8, 9, 11, 12 SOT702-1 A1, K1 B2, B1, C2, C1, D2, D1, E2, E1 SOT1134-1 A30, A13 B20, A31, D5, D1, A2, B2, B3, A5 A6, B5, B6, A9, D2, D6, A12, B8 direction control data input or output data input or output ground (0 V) supply voltage B (nBn inputs are referenced to VCC(B)) output enable input (active LOW) data input or output Description 13, 14, 16, 17, 19, 20, F1, F2, G1, G2, 22, 23 H1, H2, J1, J2 4, 10, 15, 21, 28, 34, 39, 45 7, 18 48, 25 B3, D3, G3, J3, J4, A32, A3, A8, A11, G4, D4, B4 A16, A19, A24, A27 C3, H3 A6, K6 A1, A10 A29, A14 B18, A28, D8, D4, A25, B16, B15, A22 47, 46, 44, 43, 41, 40, B5, B6, C5, C6, 38, 37 D5, D6, E5, E6 36, 35, 33, 32, 30, 29, F6, F5, G6, G5, 27, 26 H6, H5, J6, J5 31, 42 C4, H4 A21, B13, B12, A18, data input or output D3, D7, A15, B10 A17, A26 supply voltage A (nAn, nOE and nDIR inputs are referenced to VCC(A)) A2, A3, A4, A5, K2, A4, A7, A20, A23, not connected K3, K4, K5 B1, B4, B7, B9, B11, B14, B17, B19 [1] All GND pins must be connected to ground (0 V). 6. Functional description Table 3. Function table[1] Input nOE[2] L L H X nDIR[2] L H X X Input/output[3] nAn[2] nAn = nBn input Z Z nBn[2] input nBn = nAn Z Z Supply voltage VCC(A), VCC(B) 0.8 V to 3.6 V 0.8 V to 3.6 V 0.8 V to 3.6 V GND[3] [1] [2] [3] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B). If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 6 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC(A) VCC(B) IIK VI IOK VO IO ICC IGND Tstg Ptot Parameter supply voltage A supply voltage B input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Tamb = 40 C to +125 C; TSSOP48 package VFBGA56 package HXQFN60U package [1] [2] [3] [4] [5] [4] [5] [5] Conditions Min 0.5 0.5 Max +4.6 +4.6 +4.6 VCCO + 0.5 +4.6 50 100 +150 500 1000 1000 Unit V V mA V mA V V mA mA mA C mW mW mW VI < 0 V [1] 50 0.5 50 [1][2][3] [1] [2] VO < 0 V Active mode Suspend or 3-state mode VO = 0 V to VCCO ICC(A) or ICC(B) 0.5 0.5 100 65 - The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 4.6 V. Above 60 C the value of Ptot derates linearly with 5.5 mW/K. Above 70 C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC(A) VCC(B) VI VO Tamb t/V [1] [2] Recommended operating conditions Parameter supply voltage A supply voltage B input voltage output voltage ambient temperature input transition rise and fall rate VCCI = 0.8 V to 3.6 V [2] Conditions Min 0.8 0.8 0 Max 3.6 3.6 3.6 VCCO 3.6 +125 5 Unit V V V V V C ns/V Active mode Suspend or 3-state mode [1] 0 0 40 - VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 7 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 9. Static characteristics Table 6. Typical static characteristics at Tamb = 25 C[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH VOL II IOZ HIGH-level output voltage LOW-level output voltage input leakage current OFF-state output current Conditions VI = VIH or VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V VI = VIH or VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V CI CI/O input capacitance input/output capacitance nDIR, nOE input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V A and B port; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V [3] Min - Typ 0.69 0.07 Max - Unit V V 0.025 0.25 A 0.5 0.5 0.5 0.1 0.1 2.0 4.5 2.5 2.5 2.5 1 1 A A A A A pF pF [3] [3] [1] [2] [3] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the data input port. For I/O ports, the parameter IOZ includes the input leakage current. Table 7. Static characteristics [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V nDIR, nOE input VCC(A) = 0.8 V VCC(A) = 1.1 V to 1.95 V VCC(A) = 2.3 V to 2.7 V VCC(A) = 3.0 V to 3.6 V 0.70VCC(A) 0.65VCC(A) 1.6 2 0.70VCC(A) 0.65VCC(A) 1.6 2 V V V V 0.70VCCI 0.65VCCI 1.6 2 0.70VCCI 0.65VCCI 1.6 2 V V V V 40 C to +85 C Min Max 40 C to +125 C Min Max Unit 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 8 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage Conditions data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V nDIR, nOE input VCC(A) = 0.8 V VCC(A) = 1.1 V to 1.95 V VCC(A) = 2.3 V to 2.7 V VCC(A) = 3.0 V to 3.6 V VOH HIGH-level VI = VIH or VIL output voltage IO = 100 A; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V VOL LOW-level VI = VIH or VIL output voltage IO = 100 A; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V II IOZ input leakage current OFF-state output current nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V 74AVC16T245 40 C to +85 C Min VCCO  0.1 0.85 1.05 1.2 1.75 2.3 Max 0.30VCCI 0.35VCCI 0.7 0.8 0.30VCC(A) 0.35VCC(A) 0.7 0.8 - 40 C to +125 C Min VCCO  0.1 0.85 1.05 1.2 1.75 2.3 Max 0.30VCCI 0.35VCCI 0.7 0.8 Unit V V V V 0.30VCC(A) V 0.35VCC(A) V 0.7 0.8 V V V V V V V V [3] 0.1 0.25 0.35 0.45 0.55 0.7 1 5 5 - 0.1 0.25 0.35 0.45 0.55 0.7 5 30 30 V V V V V V A A A - [3] [3] - 5 - 30 A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 9 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOFF power-off leakage current Conditions A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = 0 V or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V [1] [2] [3] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the data input port. For I/O ports, the parameter IOZ includes the input leakage current. 40 C to +85 C Min Max 5 5 40 C to +125 C Min Max 30 30 Unit A A ICC supply current A port; VI = 0 V or VCCI; IO = 0 A 5 5 30 25 25 30 25 25 55 20 20 125 100 100 125 100 100 185 A A A A A A A A A - 45 - 150 A Table 8. VCC(A) 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V Typical total supply current (ICC(A) + ICC(B)) VCC(B) 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 0.8 V 0.1 0.1 0.1 0.1 0.1 0.3 1.6 1.2 V 0.1 0.1 0.1 0.1 0.1 0.1 0.8 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.4 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.2 2.5 V 0.1 0.3 0.1 0.1 0.1 0.1 0.1 3.3 V 0.1 1.6 0.8 0.4 0.2 0.1 0.1 A A A A A A A Unit 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 10 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 10. Dynamic characteristics Table 9. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter CPD power dissipation capacitance Conditions 0.8 V A port: (direction nAn to nBn); output enabled A port: (direction nAn to nBn); output disabled A port: (direction nBn to nAn); output enabled A port: (direction nBn to nAn); output disabled B port: (direction nAn to nBn); output enabled B port: (direction nAn to nBn); output disabled B port: (direction nBn to nAn); output enabled B port: (direction nBn to nAn); output disabled [1] PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL =  . VCC(A) = VCC(B) 1.2 V 0.2 0.2 9.7 0.6 9.7 0.6 0.2 0.2 1.5 V 0.2 0.2 9.8 0.6 9.8 0.6 0.2 0.2 1.8 V 0.2 0.2 10.3 0.7 10.3 0.7 0.2 0.2 2.5 V 0.3 0.3 11.7 0.7 11.7 0.7 0.3 0.3 3.3 V 0.4 0.4 13.7 0.7 13.7 0.7 0.4 0.4 0.2 0.2 9 0.6 9 0.6 0.2 0.2 Unit pF pF pF pF pF pF pF pF CPD is used to determine the dynamic power dissipation (PD in W). 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 11 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Table 10. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter tpd tdis ten Conditions 0.8 V propagation delay nAn to nBn nBn to nAn disable time enable time nOE to nAn nOE to nBn nOE to nAn nOE to nBn [1] VCC(B) 1.2 V 7.0 12.4 16.2 10.0 21.9 11.1 1.5 V 6.2 12.1 16.2 9.0 21.9 9.8 1.8 V 6.0 11.9 16.2 9.1 21.9 9.4 2.5 V 5.9 11.8 16.2 8.7 21.9 9.4 3.3 V 6.0 11.8 16.2 9.3 21.9 9.6 14.4 14.4 16.2 17.6 21.9 22.2 Unit ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 11. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter tpd tdis ten Conditions 0.8 V propagation delay nAn to nBn nBn to nAn disable time enable time nOE to nAn nOE to nBn nOE to nAn nOE to nBn [1] VCC(A) 1.2 V 12.4 7.0 5.9 14.2 6.4 17.7 1.5 V 12.1 6.2 4.4 13.7 4.4 17.2 1.8 V 11.9 6.0 4.2 13.6 3.5 17.0 2.5 V 11.8 5.9 3.1 13.3 2.6 16.8 3.3 V 11.8 6.0 3.5 13.1 2.3 16.7 14.4 14.4 16.2 17.6 21.9 22.2 Unit ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 12 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7. Symbol Parameter Conditions 1.2 V  0.1 V Min VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn VCC(A) = 1.4 V to 1.6 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn VCC(A) = 2.3 V to 2.7 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn VCC(A) = 3.0 V to 3.6 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn [1] VCC(B) 1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V Min 0.5 0.5 1.5 1.5 1.0 1.1 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 1.0 0.5 0.5 Max 6.9 8.7 11.6 9.7 14.5 11.0 6.2 6.2 9.1 8.7 10.1 10.1 5.9 5.2 7.7 8.4 7.8 9.2 5.6 4.1 6.1 7.9 5.3 9.4 5.5 3.7 5.0 7.7 4.3 9.3 Min 0.5 0.5 1.5 1.5 1.0 1.1 0.5 0.5 1.5 1.5 1.0 0.5 0.5 0.5 1.5 1.5 1.0 0.5 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 1.0 0.5 0.5 Max 6.0 8.5 11.6 9.5 14.5 9.6 5.2 5.9 9.1 7.5 10.1 8.1 4.8 4.8 7.7 7.1 7.8 7.4 4.6 3.7 6.1 6.6 5.3 7.3 4.4 3.3 5.0 6.5 4.2 7.2 Min 0.5 0.5 1.5 1.0 1.0 1.0 0.5 0.5 1.5 1.0 1.0 0.5 0.5 0.5 1.5 1.0 1.0 0.5 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 1.0 0.5 0.5 Max 5.1 8.2 11.6 8.1 14.5 8.1 4.1 5.6 9.1 6.5 10.1 5.9 3.7 4.5 7.7 5.9 7.8 5.3 3.3 3.4 6.1 6.1 5.3 5.1 3.2 2.9 5.0 5.2 4.1 4.9 3.3 V  0.3 V Min 0.5 0.5 1.5 1.0 1.0 1.0 0.5 0.5 1.5 1.0 1.0 0.5 0.5 0.5 1.5 1.0 1.0 0.5 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 4.9 8.0 11.6 8.9 14.5 7.7 3.7 5.5 9.1 6.3 10.1 5.2 3.3 4.4 7.7 5.7 7.8 4.5 2.8 3.2 6.1 5.2 5.3 4.5 2.7 2.7 5.0 5.0 4.0 4.0 Max 9.2 9.2 11.6 12.5 14.5 14.9 8.7 6.9 9.1 11.4 10.1 13.5 8.5 6.0 7.7 11.1 7.8 13.0 8.2 5.1 6.1 10.6 5.3 12.5 8.0 4.9 5.0 10.3 4.3 12.4 Unit 0.5 0.5 1.5 1.5 1.0 1.1 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 1.0 0.5 0.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 13 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter Conditions 1.2 V  0.1 V Min VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn VCC(A) = 1.4 V to 1.6 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn VCC(A) = 2.3 V to 2.7 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn VCC(A) = 3.0 V to 3.6 V tpd tdis ten propagation delay disable time enable time nAn to nBn nBn to nAn nOE to nAn nOE to nBn nOE to nAn nOE to nBn [1] VCC(B) 1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V Min 0.5 0.5 1.5 1.5 1.0 1.1 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 1.0 0.5 0.5 Max 7.6 9.6 12.8 10.7 16.0 12.1 6.9 6.9 10.1 9.6 11.2 11.2 6.5 5.8 8.5 9.3 8.6 10.2 6.2 4.6 6.8 8.7 5.9 10.4 6.1 4.1 5.5 8.5 4.8 10.3 Min 0.5 0.5 1.5 1.5 1.0 1.1 0.5 0.5 1.5 1.5 1.0 0.5 0.5 0.5 1.5 1.5 1.0 0.5 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 1.0 0.5 0.5 Max 6.6 9.4 12.8 10.5 16.0 10.6 5.8 6.5 10.1 8.3 11.2 9.0 5.3 5.3 8.5 7.9 8.6 8.2 5.1 4.1 6.8 7.3 5.9 8.1 4.9 3.7 5.5 7.2 4.7 8.0 Min 0.5 0.5 1.5 1.0 1.0 1.0 0.5 0.5 1.5 1.0 1.0 0.5 0.5 0.5 1.5 1.0 1.0 0.5 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 1.0 0.5 0.5 Max 5.7 9.1 12.8 9.0 16.0 9.0 4.6 6.2 10.1 7.2 11.2 6.5 4.1 5.0 8.5 6.5 8.6 5.9 3.7 3.8 6.8 6.8 5.9 5.7 3.6 3.2 5.5 5.8 4.6 5.4 3.3 V  0.3 V Min 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.5 1.0 1.0 0.5 0.5 0.5 1.5 1.0 1.0 0.5 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 5.4 8.8 12.8 9.8 16.0 8.5 4.1 6.1 10.1 7.0 11.2 5.8 3.7 4.9 8.5 6.3 8.6 5.0 3.1 3.6 6.8 5.8 5.9 5.0 3.0 3.0 5.5 5.5 4.4 4.4 Max 10.2 10.2 12.8 13.8 16.0 16.4 9.6 7.6 10.1 12.6 11.2 14.9 9.4 6.6 8.5 12.3 8.6 14.3 9.1 5.7 6.8 11.7 5.9 13.8 8.8 5.4 5.5 11.4 4.8 13.7 Unit 0.5 0.5 1.5 1.5 1.0 1.1 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.5 1.5 1.0 1.0 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 1.0 0.5 0.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 14 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 11. Waveforms VI nAn, nBn input GND VM tPHL VOH nBn, nAn output VOL tPLH VM 001aak285 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times VI nOE input GND tPLZ VCCO output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aak286 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 14. Enable and disable times Measurement points Input[1] VM 0.5VCCI 0.5VCCI 0.5VCCI Output[2] VM 0.5VCCO 0.5VCCO 0.5VCCO VX VOL + 0.1 V VOL + 0.15 V VOL + 0.3 V VY VOH  0.1 V VOH  0.15 V VOH  0.3 V Supply voltage VCC(A), VCC(B) 0.8 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 15 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 8. Table 15. Load circuit for switching times Test data Input VI[1] VCCI VCCI VCCI t/V[2] 1.0 ns/V  1.0 ns/V  1.0 ns/V Load CL 15 pF 15 pF 15 pF RL 2 k 2 k 2 k VEXT tPLH, tPHL open open open tPZH, tPHZ GND GND GND tPZL, tPLZ[3] 2VCCO 2VCCO 2VCCO Supply voltage VCC(A), VCC(B) 0.8 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] [3] VCCI is the supply voltage associated with the data input port. dV/dt  1.0 V/ns VCCO is the supply voltage associated with the output port. 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 16 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 12. Typical propagation delay characteristics 001aai476 001aai477 (1) (2) (3) (4) (5) (6) 24 tpd (ns) 20 21 tpd (ns) 17 (1) 16 12 (2) (3) (4) (5) (6) 13 8 4 0 20 40 CL (pF) 60 9 0 20 40 CL (pF) 60 a. Propagation delay (nAn to nBn); VCC(A) = 0.8 V (1) VCC(B) = 0.8 V. (2) VCC(B) = 1.2 V. (3) VCC(B) = 1.5 V. (4) VCC(B) = 1.8 V. (5) VCC(B) = 2.5 V. (6) VCC(B) = 3.3 V. b. Propagation delay (nAn to nBn); VCC(B) = 0.8 V (1) VCC(A) = 0.8 V. (2) VCC(A) = 1.2 V. (3) VCC(A) = 1.5 V. (4) VCC(A) = 1.8 V. (5) VCC(A) = 2.5 V. (6) VCC(A) = 3.3 V. Fig 9. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 17 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 7 tPLH (ns) 5 001aai478 (1) 7 tPHL (ns) 001aai491 (1) (2) (3) (4) (5) 5 (2) (3) (4) (5) 3 3 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.2 V 7 tPLH (ns) 5 001aai479 (1) b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.2 V 7 tPHL (ns) (1) 001aai480 (2) (3) (4) 5 (2) (3) 3 (5) 3 (4) (5) 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.5 V Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 18 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 7 tPLH (ns) 5 001aai481 7 tPHL (ns) 5 001aai482 (1) (1) (2) (3) (4) (2) (3) 3 (5) 3 (4) (5) 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.8 V 7 tPLH (ns) 5 (2) (3) (4) (5) 001aai483 b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.8 V 7 tPHL (ns) 5 (1) 001aai486 (1) (2) (3) 3 3 (4) (5) 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 2.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 2.5 V Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 19 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 7 tPLH (ns) 5 001aai485 7 tPHL (ns) 5 001aai484 (1) (1) (2) (2) (3) (3) 3 (4) (5) 3 (4) (5) 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 3.3 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 3.3 V Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 20 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 13. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c y HE vMA Z 48 25 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp 24 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT362-1 (TSSOP48) 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 21 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1 D E A X c y HE vMA Z 48 25 Q A2 A1 pin 1 index Lp L detail X θ (A 3) A 1 e bp 24 wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.23 0.13 c 0.20 0.09 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.4 HE 6.6 6.2 L 1 Lp 0.7 0.5 Q 0.4 0.3 v 0.2 w 0.07 y 0.08 Z (1) 0.4 0.1 θ 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT480-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 14. Package outline SOT480-1 (TSSOP48) 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 22 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm SOT702-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 b e CAB ∅w M C ∅v M C y1 C y K J H e G F E D C B A ball A1 index area 1 2 3 4 5 6 1/2 e2 e X DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.3 0.2 A2 0.7 0.6 b 0.45 0.35 D 4.6 4.4 E 7.1 6.9 e 0.65 e1 3.25 e2 5.85 v 0.15 w 0.08 y 0.08 y1 0.1 0 2.5 scale 5 mm OUTLINE VERSION SOT702-1 REFERENCES IEC JEDEC MO-225 JEITA EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 Fig 15. Package outline SOT702-1 (VFBGA56) 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 23 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm D B A SOT1134-1 terminal 1 index area E A A1 detail X e2 e1 1/2 e v w L1 CAB C D2 D6 A10 eR B7 e b A11 B8 B10 A16 D7 A17 B11 D3 v w CAB C y1 C C y L e Eh 1/2 e B1 A1 terminal 1 index area D5 D1 B20 A32 Dh k 0 Dimensions Unit mm A A1 b D 4.1 4.0 3.9 Dh 1.90 1.85 1.80 E 6.1 6.0 5.9 Eh 3.90 3.85 3.80 e 0.5 e1 1 2.5 scale e2 2.5 B18 A27 D8 D4 B17 A26 e3 e4 X 5 mm e3 3 e4 4.5 eR 0.5 k L L1 0.125 0.075 0.025 v w y y1 0.1 sot1134-1_po max 0.50 0.05 0.35 nom 0.48 0.02 0.30 min 0.46 0.00 0.25 0.25 0.35 0.20 0.30 0.15 0.25 0.07 0.05 0.08 Outline version SOT1134-1 References IEC --JEDEC --JEITA --- European projection Issue date 08-12-17 09-01-22 Fig 16. Package outline SOT1134-1 (HXQFN60U) 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 24 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 14. Abbreviations Table 16. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 17. Revision history Release date 20110609 Data sheet status Product data sheet Product data sheet Change notice Supersedes 74AVC16T245 v.2 74AVC16T245 v.1 Document ID 74AVC16T245 v.3 Modifications: 74AVC16T245 v.2 Modifications: 74AVC16T245 v.1 • • 74AVC16T245BQ changed to 74AVC16T245BX for HXQFN60U (SOT1134-1) package. 74AVC16T245BQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. Product data sheet - 20100330 20091001 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 25 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 26 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AVC16T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 June 2011 27 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Typical propagation delay characteristics . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Contact information. . . . . . . . . . . . . . . . . . . . . 27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 June 2011 Document identifier: 74AVC16T245