74AVC16T245DGV,112

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74AVC16T245 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 6 — 9 September 2013 Product data sheet 1. General description The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn are in the high-impedance OFF-state. 2. Features and benefits  Wide supply voltage range:  VCC(A): 0.8 V to 3.6 V  VCC(B): 0.8 V to 3.6 V  Complies with JEDEC standards:  JESD8-12 (0.8 V to 1.3 V)  JESD8-11 (0.9 V to 1.65 V)  JESD8-7 (1.2 V to 1.95 V)  JESD8-5 (1.8 V to 2.7 V)  JESD8-B (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F Class 3B exceeds 8000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101D exceeds 1000 V  Maximum data rates:  380 Mbit/s ( 1.8 V to 3.3 V translation)  200 Mbit/s ( 1.1 V to 3.3 V translation)  200 Mbit/s ( 1.1 V to 2.5 V translation)  200 Mbit/s ( 1.1 V to 1.8 V translation)  150 Mbit/s ( 1.1 V to 1.5 V translation) 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state  100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C and 40 C to +125 C       3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74AVC16T245DGG 40 C to +125 C TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm 74AVC16T245DGV 40 C to +125 C TSSOP48[1] plastic thin shrink small outline package; 48 leads; SOT480-1 body width 4.4 mm; lead pitch 0.4 mm 74AVC16T245EV 40 C to +125 C VFBGA56 plastic very thin fine-pitch ball grid array package; SOT702-1 56 balls; body 4.5  7  0.65 mm 74AVC16T245BX 40 C to +125 C HXQFN60 plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 4  6  0.5 mm [1] Version SOT1134-2 Also known as TVSOP48. 4. Functional diagram 1DIR 2DIR 1OE 1A1 2OE 2A1 1B1 VCC(A) VCC(B) 2B1 VCC(A) to other seven channels Fig 1. VCC(B) to other seven channels 001aak426 Logic diagram 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 2 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 1B1 VCC(A) 1B2 1B3 1B4 1B5 1B6 1B7 1B8 VCC(B) 1OE 1DIR 1A1 1A2 2B1 VCC(A) 1A3 2B2 1A4 2B3 1A5 2B4 1A6 2B5 1A7 2B6 1A8 2B7 2B8 VCC(B) 2OE 2DIR 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 001aak425 Fig 2. Logic symbol 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 3 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 5. Pinning information 5.1 Pinning 74AVC16T245 1DIR 1 48 1OE 1B1 2 47 1A1 1B2 3 46 1A2 GND 4 45 GND 1B3 5 44 1A3 1B4 6 43 1A4 VCC(B) 7 42 VCC(A) 1B5 8 41 1A5 1B6 9 40 1A6 GND 10 39 GND 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 14 35 2A2 GND 15 34 GND 2B3 16 33 2A3 2B4 17 32 2A4 VCC(B) 18 ball A1 74AVC16T245 index area 1 2 3 4 5 6 A B C D E F G H J K 31 VCC(A) 2B5 19 30 2A5 2B6 20 29 2A6 GND 21 28 GND 2B7 22 27 2A7 2B8 23 26 2A8 2DIR 24 25 2OE 001aak428 Transparent top view 001aak427 Fig 3. Pin configuration SOT362-1 and SOT480-1 (TSSOP48) 74AVC16T245 Product data sheet Fig 4. Pin configuration SOT702-1 (VFBGA56) All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 4 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state terminal 1 index area D1 A32 A1 D5 A31 A30 B20 A29 B19 A28 B18 A27 D4 D8 A26 A2 A25 B1 B17 B2 B16 A3 A24 A4 A23 B15 B3 A5 A22 74AVC16T245 B4 B14 A6 A21 B5 B13 B6 B12 A20 A7 A8 A19 B7 B11 A9 A18 GND(1) A10 D6 D2 A11 B8 A12 B9 A13 B10 A14 A15 D7 A17 A16 D3 001aak429 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SOT1134-2 (HXQFN60) 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 5 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description SOT362-1 and SOT480-1 SOT702-1 SOT1134-2 1DIR, 2DIR 1, 24 A1, K1 A30, A13 direction control 1B1 to 1B8 2, 3, 5, 6, 8, 9, 11, 12 B2, B1, C2, C1, D2, D1, E2, E1 B20, A31, D5, D1, A2, B2, B3, A5 data input or output 2B1 to 2B8 13, 14, 16, 17, 19, 20, F1, F2, G1, G2, 22, 23 H1, H2, J1, J2 A6, B5, B6, A9, D2, D6, A12, B8 data input or output GND[1] 4, 10, 15, 21, 28, 34, 39, 45 B3, D3, G3, J3, J4, A32, A3, A8, A11, G4, D4, B4 A16, A19, A24, A27 ground (0 V) VCC(B) 7, 18 C3, H3 A1, A10 supply voltage B (nBn inputs are referenced to VCC(B)) 1OE, 2OE 48, 25 A6, K6 A29, A14 output enable input (active LOW) 1A1 to 1A8 47, 46, 44, 43, 41, 40, B5, B6, C5, C6, 38, 37 D5, D6, E5, E6 B18, A28, D8, D4, A25, B16, B15, A22 data input or output 2A1 to 2A8 36, 35, 33, 32, 30, 29, F6, F5, G6, G5, 27, 26 H6, H5, J6, J5 A21, B13, B12, A18, data input or output D3, D7, A15, B10 VCC(A) 31, 42 C4, H4 A17, A26 n.c. - A2, A3, A4, A5, K2, A4, A7, A20, A23, not connected K3, K4, K5 B1, B4, B7, B9, B11, B14, B17, B19 [1] supply voltage A (nAn, nOE and nDIR inputs are referenced to VCC(A)) All GND pins must be connected to ground (0 V). 6. Functional description Table 3. Function table[1] Input/output[3] Supply voltage Input VCC(A), VCC(B) nOE[2] nDIR[2] nAn[2] nBn[2] 0.8 V to 3.6 V L L nAn = nBn input 0.8 V to 3.6 V L H input nBn = nAn 0.8 V to 3.6 V H X Z Z GND[3] X X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B). [3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 6 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) supply voltage A VCC(B) supply voltage B IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit 0.5 +4.6 V 0.5 +4.6 V 50 - mA 0.5 +4.6 V mA 50 - [1][2][3] 0.5 VCCO + 0.5 V Suspend or 3-state mode [1] 0.5 +4.6 V [2] - 50 mA 100 mA VO < 0 V Active mode IO output current VO = 0 V to VCCO ICC supply current per VCC(A) or VCC(B) pin - per GND pin 100 - mA 65 +150 C IGND ground current Tstg storage temperature Ptot total power dissipation [1] Tamb = 40 C to +125 C; TSSOP48 package [4] - 500 mW VFBGA56 package [5] - 1000 mW HXQFN60 package [5] - 1000 mW The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 4.6 V. [4] Above 60 C the value of Ptot derates linearly with 5.5 mW/K. [5] Above 70 C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC(A) Conditions Min Max Unit supply voltage A 0.8 3.6 V VCC(B) supply voltage B 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage 0 VCCO V 0 3.6 V 40 +125 C - 5 ns/V Active mode [1] Suspend or 3-state mode Tamb t/V ambient temperature input transition rise and fall rate VCCI = 0.8 V to 3.6 V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 [2] © NXP B.V. 2013. All rights reserved. 7 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 9. Static characteristics Table 6. Typical static characteristics at Tamb = 25 C[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL VOL LOW-level output voltage VI = VIH or VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V Min Typ Max Unit - 0.69 - V - 0.07 - V - 0.025 0.25 A II input leakage current nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V [3] - 0.5 2.5 A suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V [3] - 0.5 2.5 A suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V [3] - 0.5 2.5 A A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - 0.1 1 A B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - 0.1 1 A IOFF power-off leakage current CI input capacitance nDIR, nOE input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 2.0 - pF CI/O input/output capacitance A and B port; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - 4.5 - pF [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter IOZ includes the input leakage current. Table 7. Static characteristics [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCCI = 0.8 V 0.70VCCI - 0.70VCCI - V VCCI = 1.1 V to 1.95 V 0.65VCCI - 0.65VCCI - V VCCI = 2.3 V to 2.7 V 1.6 - 1.6 - V VCCI = 3.0 V to 3.6 V 2 - 2 - V VCC(A) = 0.8 V 0.70VCC(A) - 0.70VCC(A) - V VCC(A) = 1.1 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCC(A) = 2.3 V to 2.7 V 1.6 - 1.6 - V VCC(A) = 3.0 V to 3.6 V 2 - 2 - V data input nDIR, nOE input 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 8 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage 40 C to +85 C Conditions 40 C to +125 C Min Max Min Max Unit data input VCCI = 0.8 V - 0.30VCCI - 0.30VCCI V VCCI = 1.1 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V VCC(A) = 0.8 V - 0.30VCC(A) - 0.30VCC(A) V VCC(A) = 1.1 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V VCC(A) = 3.0 V to 3.6 V - 0.8 - 0.8 V VCCO  0.1 - VCCO  0.1 - V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V 0.85 - 0.85 - V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V 1.05 - 1.05 - V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V 1.2 - 1.2 - V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V 1.75 - 1.75 - V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V 2.3 - 2.3 - V - 0.1 - 0.1 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V - 0.25 - 0.25 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V - 0.35 - 0.35 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V - 0.45 - 0.45 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V - 0.55 - 0.55 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V - 0.7 - 0.7 V - 1 - 5 A nDIR, nOE input VOH VOL HIGH-level VI = VIH or VIL output voltage IO = 100 A; VCC(A) = VCC(B) = 0.8 V to 3.6 V LOW-level VI = VIH or VIL output voltage IO = 100 A; VCC(A) = VCC(B) = 0.8 V to 3.6 V II input leakage current nDIR, nOE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V [3] - 5 - 30 A suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V [3] - 5 - 30 A suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V [3] - 5 - 30 A 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 9 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOFF power-off leakage current 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V - 5 - 30 A B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - 5 - 30 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 30 - 125 A VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 25 - 100 A VCC(A) = 3.6 V; VCC(B) = 0 V - 25 - 100 A VCC(A) = 0 V; VCC(B) = 3.6 V 5 - 20 - A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 30 - 125 A VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 25 - 100 A VCC(A) = 3.6 V; VCC(B) = 0 V 5 - 20 - A VCC(A) = 0 V; VCC(B) = 3.6 V supply current A port; VI = 0 V or VCCI; IO = 0 A ICC B port; VI = 0 V or VCCI; IO = 0 A - 25 - 100 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 55 - 185 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 45 - 150 A [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter IOZ includes the input leakage current. Table 8. VCC(A) Typical total supply current (ICC(A) + ICC(B)) VCC(B) Unit 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 A 0.8 V 0.1 0.1 0.1 0.1 0.1 0.3 1.6 A 1.2 V 0.1 0.1 0.1 0.1 0.1 0.1 0.8 A 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.4 A 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.2 A 2.5 V 0.1 0.3 0.1 0.1 0.1 0.1 0.1 A 3.3 V 0.1 1.6 0.8 0.4 0.2 0.1 0.1 A 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 10 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 10. Dynamic characteristics Table 9. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter power dissipation capacitance CPD [1] Conditions VCC(A) = VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V A port: (direction nAn to nBn); output enabled 0.2 0.2 0.2 0.2 0.3 0.4 pF A port: (direction nAn to nBn); output disabled 0.2 0.2 0.2 0.2 0.3 0.4 pF A port: (direction nBn to nAn); output enabled 9 9.7 9.8 10.3 11.7 13.7 pF A port: (direction nBn to nAn); output disabled 0.6 0.6 0.6 0.7 0.7 0.7 pF B port: (direction nAn to nBn); output enabled 9 9.7 9.8 10.3 11.7 13.7 pF B port: (direction nAn to nBn); output disabled 0.6 0.6 0.6 0.7 0.7 0.7 pF B port: (direction nBn to nAn); output enabled 0.2 0.2 0.2 0.2 0.3 0.4 pF B port: (direction nBn to nAn); output disabled 0.2 0.2 0.2 0.2 0.3 0.4 pF CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL =  . 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 11 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state Table 10. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter tpd VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V propagation delay nAn to nBn 14.4 7.0 6.2 6.0 5.9 6.0 ns nBn to nAn 14.4 12.4 12.1 11.9 11.8 11.8 ns nOE to nAn 16.2 16.2 16.2 16.2 16.2 16.2 ns tdis disable time ten enable time [1] Conditions nOE to nBn 17.6 10.0 9.0 9.1 8.7 9.3 ns nOE to nAn 21.9 21.9 21.9 21.9 21.9 21.9 ns nOE to nBn 22.2 11.1 9.8 9.4 9.4 9.6 ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 11. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter tpd VCC(A) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V propagation delay nAn to nBn 14.4 12.4 12.1 11.9 11.8 11.8 ns nBn to nAn 14.4 7.0 6.2 6.0 5.9 6.0 ns nOE to nAn 16.2 5.9 4.4 4.2 3.1 3.5 ns nOE to nBn 17.6 14.2 13.7 13.6 13.3 13.1 ns nOE to nAn 21.9 6.4 4.4 3.5 2.6 2.3 ns nOE to nBn 22.2 17.7 17.2 17.0 16.8 16.7 ns tdis disable time ten enable time [1] Conditions tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 12 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7. Symbol Parameter Conditions VCC(B) Unit 1.2 V  0.1 V 1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V Min Max Min Max Min Max Min Max Min Max 9.2 0.5 6.9 0.5 6.0 0.5 5.1 0.5 4.9 ns VCC(A) = 1.1 V to 1.3 V tpd propagation delay nAn to nBn 0.5 nBn to nAn 0.5 9.2 0.5 8.7 0.5 8.5 0.5 8.2 0.5 8.0 ns tdis disable time nOE to nAn 1.5 11.6 1.5 11.6 1.5 11.6 1.5 11.6 1.5 11.6 ns nOE to nBn 1.5 12.5 1.5 9.7 1.5 9.5 1.0 8.1 1.0 8.9 ns nOE to nAn 1.0 14.5 1.0 14.5 1.0 14.5 1.0 14.5 1.0 14.5 ns nOE to nBn 1.1 14.9 1.1 11.0 1.1 9.6 1.0 8.1 1.0 7.7 ns propagation delay nAn to nBn 0.5 8.7 0.5 6.2 0.5 5.2 0.5 4.1 0.5 3.7 ns nBn to nAn 0.5 6.9 0.5 6.2 0.5 5.9 0.5 5.6 0.5 5.5 ns disable time nOE to nAn 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1 ns nOE to nBn 1.5 11.4 1.5 8.7 1.5 7.5 1.0 6.5 1.0 6.3 ns nOE to nAn 1.0 10.1 1.0 10.1 1.0 10.1 1.0 10.1 1.0 10.1 ns nOE to nBn 1.0 13.5 1.0 10.1 0.5 8.1 0.5 5.9 0.5 5.2 ns enable time ten VCC(A) = 1.4 V to 1.6 V tpd tdis enable time ten VCC(A) = 1.65 V to 1.95 V propagation delay nAn to nBn 0.5 8.5 0.5 5.9 0.5 4.8 0.5 3.7 0.5 3.3 ns nBn to nAn 0.5 6.0 0.5 5.2 0.5 4.8 0.5 4.5 0.5 4.4 ns tdis disable time nOE to nAn 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7 ns nOE to nBn 1.5 11.1 1.5 8.4 1.5 7.1 1.0 5.9 1.0 5.7 ns ten enable time nOE to nAn 1.0 7.8 1.0 7.8 1.0 7.8 1.0 7.8 1.0 7.8 ns nOE to nBn 1.0 13.0 1.0 9.2 0.5 7.4 0.5 5.3 0.5 4.5 ns propagation delay nAn to nBn 0.5 8.2 0.5 5.6 0.5 4.6 0.5 3.3 0.5 2.8 ns nBn to nAn 0.5 5.1 0.5 4.1 0.5 3.7 0.5 3.4 0.5 3.2 ns disable time nOE to nAn 1.0 6.1 1.0 6.1 1.0 6.1 1.0 6.1 1.0 6.1 ns nOE to nBn 1.0 10.6 1.0 7.9 1.0 6.6 1.0 6.1 1.0 5.2 ns tpd VCC(A) = 2.3 V to 2.7 V tpd tdis enable time ten nOE to nAn 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3 ns nOE to nBn 0.5 12.5 0.5 9.4 0.5 7.3 0.5 5.1 0.5 4.5 ns 0.5 8.0 0.5 5.5 0.5 4.4 0.5 3.2 0.5 2.7 ns VCC(A) = 3.0 V to 3.6 V tpd propagation delay nAn to nBn nBn to nAn 0.5 4.9 0.5 3.7 0.5 3.3 0.5 2.9 0.5 2.7 ns tdis disable time nOE to nAn 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 ns nOE to nBn 1.0 10.3 1.0 7.7 1.0 6.5 1.0 5.2 0.5 5.0 ns nOE to nAn 0.5 4.3 0.5 4.3 0.5 4.2 0.5 4.1 0.5 4.0 ns nOE to nBn 0.5 12.4 0.5 9.3 0.5 7.2 0.5 4.9 0.5 4.0 ns enable time ten [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 13 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7 Symbol Parameter Conditions VCC(B) Unit 1.2 V  0.1 V 1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V Min Max Min Max Min Max Min Max Min Max 0.5 10.2 0.5 7.6 0.5 6.6 0.5 5.7 0.5 5.4 ns VCC(A) = 1.1 V to 1.3 V tpd propagation delay nAn to nBn nBn to nAn 0.5 10.2 0.5 9.6 0.5 9.4 0.5 9.1 0.5 8.8 ns tdis disable time nOE to nAn 1.5 12.8 1.5 12.8 1.5 12.8 1.5 12.8 1.5 12.8 ns nOE to nBn 1.5 13.8 1.5 10.7 1.5 10.5 1.0 9.0 1.5 9.8 ns nOE to nAn 1.0 16.0 1.0 16.0 1.0 16.0 1.0 16.0 1.0 16.0 ns nOE to nBn 1.1 16.4 1.1 12.1 1.1 10.6 1.0 9.0 1.0 8.5 ns propagation delay nAn to nBn 0.5 9.6 0.5 6.9 0.5 5.8 0.5 4.6 0.5 4.1 ns nBn to nAn 0.5 7.6 0.5 6.9 0.5 6.5 0.5 6.2 0.5 6.1 ns disable time nOE to nAn 1.5 10.1 1.5 10.1 1.5 10.1 1.5 10.1 1.5 10.1 ns nOE to nBn 1.5 12.6 1.5 9.6 1.5 8.3 1.0 7.2 1.0 7.0 ns nOE to nAn 1.0 11.2 1.0 11.2 1.0 11.2 1.0 11.2 1.0 11.2 ns nOE to nBn 1.0 14.9 1.0 11.2 0.5 9.0 0.5 6.5 0.5 5.8 ns enable time ten VCC(A) = 1.4 V to 1.6 V tpd tdis enable time ten VCC(A) = 1.65 V to 1.95 V propagation delay nAn to nBn 0.5 9.4 0.5 6.5 0.5 5.3 0.5 4.1 0.5 3.7 ns nBn to nAn 0.5 6.6 0.5 5.8 0.5 5.3 0.5 5.0 0.5 4.9 ns tdis disable time nOE to nAn 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 ns nOE to nBn 1.5 12.3 1.5 9.3 1.5 7.9 1.0 6.5 1.0 6.3 ns ten enable time nOE to nAn 1.0 8.6 1.0 8.6 1.0 8.6 1.0 8.6 1.0 8.6 ns nOE to nBn 1.0 14.3 1.0 10.2 0.5 8.2 0.5 5.9 0.5 5.0 ns propagation delay nAn to nBn 0.5 9.1 0.5 6.2 0.5 5.1 0.5 3.7 0.5 3.1 ns nBn to nAn 0.5 5.7 0.5 4.6 0.5 4.1 0.5 3.8 0.5 3.6 ns disable time nOE to nAn 1.0 6.8 1.0 6.8 1.0 6.8 1.0 6.8 1.0 6.8 ns nOE to nBn 1.0 11.7 1.0 8.7 1.0 7.3 1.0 6.8 1.0 5.8 ns nOE to nAn 0.5 5.9 0.5 5.9 0.5 5.9 0.5 5.9 0.5 5.9 ns nOE to nBn 0.5 13.8 0.5 10.4 0.5 8.1 0.5 5.7 0.5 5.0 ns 0.5 8.8 0.5 6.1 0.5 4.9 0.5 3.6 0.5 3.0 ns tpd VCC(A) = 2.3 V to 2.7 V tpd tdis enable time ten VCC(A) = 3.0 V to 3.6 V tpd propagation delay nAn to nBn nBn to nAn 0.5 5.4 0.5 4.1 0.5 3.7 0.5 3.2 0.5 3.0 ns tdis disable time nOE to nAn 0.5 5.5 0.5 5.5 0.5 5.5 0.5 5.5 0.5 5.5 ns nOE to nBn 1.0 11.4 1.0 8.5 1.0 7.2 1.0 5.8 0.5 5.5 ns nOE to nAn 0.5 4.8 0.5 4.8 0.5 4.7 0.5 4.6 0.5 4.4 ns nOE to nBn 0.5 13.7 0.5 10.3 0.5 8.0 0.5 5.4 0.5 4.4 ns enable time ten [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 14 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 11. Waveforms VI nAn, nBn input VM GND tPHL tPLH VOH VM nBn, nAn output VOL 001aak285 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times VI VM nOE input GND tPLZ tPZL VCCO output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled 001aak286 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 14. Enable and disable times Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 0.8 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH  0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH  0.15 V 3.0 V to 3.6 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH  0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 15 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 8. Table 15. Test circuit for measuring switching times Test data Supply voltage Input VCC(A), VCC(B) VI[1] t/V[2] Load CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3] 0.8 V to 1.6 V VCCI 1.0 ns/V 15 pF 2 k open GND 2VCCO 1.65 V to 2.7 V VCCI  1.0 ns/V 15 pF 2 k open GND 2VCCO 3.0 V to 3.6 V VCCI  1.0 ns/V 15 pF 2 k open GND 2VCCO [1] VCCI is the supply voltage associated with the data input port. [2] dV/dt  1.0 V/ns [3] VCCO is the supply voltage associated with the output port. 74AVC16T245 Product data sheet VEXT All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 16 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 12. Typical propagation delay characteristics 001aai476 24 tpd (ns) (1) (2) (3) (4) (5) (6) tpd (ns) (1) 20 001aai477 21 17 16 12 13 (2) (3) (4) (5) (6) 8 4 9 0 20 40 60 0 20 CL (pF) 40 60 CL (pF) a. Propagation delay (nAn to nBn); VCC(A) = 0.8 V b. Propagation delay (nAn to nBn); VCC(B) = 0.8 V (1) VCC(B) = 0.8 V. (1) VCC(A) = 0.8 V. (2) VCC(B) = 1.2 V. (2) VCC(A) = 1.2 V. (3) VCC(B) = 1.5 V. (3) VCC(A) = 1.5 V. (4) VCC(B) = 1.8 V. (4) VCC(A) = 1.8 V. (5) VCC(B) = 2.5 V. (5) VCC(A) = 2.5 V. (6) VCC(B) = 3.3 V. (6) VCC(A) = 3.3 V. Fig 9. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 17 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 001aai478 7 001aai491 7 (1) tPLH (ns) tPHL (ns) (2) 5 (1) 5 (3) (2) (3) (4) (4) (5) (5) 3 3 1 1 0 20 40 60 0 20 40 CL (pF) a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.2 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.2 V 001aai479 7 60 CL (pF) 001aai480 7 (1) tPLH (ns) tPHL (ns) (1) 5 5 (2) (3) (2) (3) (4) (5) 3 (4) (5) 3 1 1 0 20 40 60 0 CL (pF) 20 40 60 CL (pF) c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.5 V d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 18 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 001aai481 7 (1) tPLH (ns) 001aai482 7 tPHL (ns) 5 (1) 5 (2) (3) (2) (3) (4) 3 (4) (5) 3 (5) 1 1 0 20 40 60 0 20 40 CL (pF) a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.8 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.8 V 001aai483 7 tPLH (ns) 60 CL (pF) 001aai486 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) (3) (4) 3 3 (4) (5) (5) 1 1 0 20 40 60 0 CL (pF) 20 40 60 CL (pF) c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 2.5 V d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 2.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 19 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 001aai485 7 tPLH (ns) 001aai484 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) (3) 3 3 (4) (4) (5) (5) 1 1 0 20 40 60 0 CL (pF) 20 40 60 CL (pF) a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 3.3 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 3.3 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 C 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 20 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 13. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 (A3) A1 A pin 1 index θ Lp L 1 24 detail X w bp e 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit max nom min mm A A1 A2 A3 0.15 1.05 1.2 bp c D(1) E(2) 0.28 0.2 12.6 6.2 HE 0.17 0.1 12.4 L 8.3 0.5 0.25 0.05 0.85 e 6.0 Lp Q 0.8 0.50 1 7.9 v w 0.25 0.08 0.4 0.35 y Z θ 0.8 8° 0.4 0° 0.1 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Fig 13. Package outline SOT362-1 (TSSOP48) 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 21 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1 E D A X c y HE v M A Z 25 48 Q (A 3) A2 A A1 pin 1 index θ Lp L detail X 1 24 w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.85 0.25 0.23 0.13 0.20 0.09 9.8 9.6 4.5 4.3 0.4 6.6 6.2 1 0.7 0.5 0.4 0.3 0.2 0.07 0.08 0.4 0.1 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT480-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 14. Package outline SOT480-1 (TSSOP48) 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 22 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm B D SOT702-1 A ball A1 index area A E A2 A1 detail X e1 1/2 C ∅v M C A B ∅w M C b e y1 C e y K J H e G F e2 E D 1/2 e C X B A ball A1 index area 1 2 3 4 5 6 DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1 0.3 0.2 0.7 0.6 0.45 0.35 4.6 4.4 7.1 6.9 0.65 3.25 5.85 0.15 0.08 0.08 0.1 OUTLINE VERSION SOT702-1 REFERENCES IEC JEDEC JEITA 0 2.5 5 mm scale EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 MO-225 Fig 15. Package outline SOT702-1 (VFBGA56) 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 23 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 4 x 6 x 0.5 mm A B D SOT1134-2 terminal 1 index area A A2 E A1 detail X e2 b e1 L1 L A11 B10 A17 A10 eR eT y y1 C D3 D7 A16 B8 C eT 1/2 e D2 D6 C A B C eR e C A B C v w v w e B11 B7 Eh e3 e4 1/2 e B17 B1 A1 terminal 1 index area A26 D5 D1 A32 B20 B18 A27 Dh D8 D4 eT eR X K eT eR 0 5 mm Dimensions Unit A A1 A2 b max 0.50 0.08 0.42 0.28 nom 0.05 0.40 0.23 min 0.02 0.38 0.18 mm D Dh E Eh e e1 e2 e3 e4 eR 4.1 4.0 3.9 1.95 1.85 1.75 6.1 6.0 5.9 3.95 3.85 3.75 0.5 1.0 2.5 3.0 4.5 0.5 eT K L L1 v w 0.25 0.28 0.195 0.49 0.20 0.23 0.145 0.1 0.15 0.18 0.095 y 0.05 0.08 y1 0.1 sot1134-2_po References Outline version IEC JEDEC JEITA SOT1134-2 --- --- --- European projection Issue date 11-08-15 Fig 16. Package outline SOT1134-2 (HXQFN60) 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 24 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 14. Abbreviations Table 16. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVC16T245 v.6 20130909 Product data sheet - 74AVC16T245 v.5 Modifications: 74AVC16T245 v.5 Modifications: 74AVC16T245 v.4 Modifications: • Table 4: conditions ICC and IGND changed (errata). 20120309 • - 74AVC16T245 v.4 For type number 74AVC16T245BX the sot code has changed to SOT1134-2. 20111208 • Product data sheet Product data sheet - 74AVC16T245 v.3 Legal pages updated. 74AVC16T245 v.3 20110609 Product data sheet - 74AVC16T245 v.2 74AVC16T245 v.2 20100330 Product data sheet - 74AVC16T245 v.1 74AVC16T245 v.1 20091001 Product data sheet - - 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 25 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74AVC16T245 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 26 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AVC16T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 9 September 2013 © NXP B.V. 2013. All rights reserved. 27 of 28 74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Typical propagation delay characteristics . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Contact information. . . . . . . . . . . . . . . . . . . . . 27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 September 2013 Document identifier: 74AVC16T245