74AVCH8T245PW

74AVCH8T245 8-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 02 — 28 April 2009 Product data sheet 1. General description The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (An and Bn), a direction control input (DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from B to A. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B outputs are in the high-impedance OFF-state. The bus-hold circuitry on the powered-up side always stays active. The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features I Wide supply voltage range: N VCC(A): 0.8 V to 3.6 V N VCC(B): 0.8 V to 3.6 V I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 3B exceeds 8000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Maximum data rates: N 380 Mbit/s (≥ 1.8 V to 3.3 V translation) N 260 Mbit/s (≥ 1.1 V to 3.3 V translation) NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state I I I I I I I N 260 Mbit/s (≥ 1.1 V to 2.5 V translation) N 210 Mbit/s (≥ 1.1 V to 1.8 V translation) N 150 Mbit/s (≥ 1.1 V to 1.5 V translation) N 100 Mbit/s (≥ 1.1 V to 1.2 V translation) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AVCH8T245PW −40 °C to +125 °C 74AVCH8T245BQ −40 °C to +125 °C TSSOP24 Description plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT355-1 Type number DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1 thin quad flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm 4. Functional diagram B1 21 VCC(A) VCC(B) B2 20 B3 19 B4 18 B5 17 B6 16 B7 15 B8 14 OE 22 DIR 2 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 A8 001aai472 Fig 1. Logic symbol 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 2 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state DIR OE A1 B1 VCC(A) VCC(B) to other seven channels 001aai473 Fig 2. Logic diagram (one channel) 5. Pinning information 5.1 Pinning 74AVCH8T245 VCC(A) terminal 1 index area 24 VCC(B) 23 VCC(B) 22 OE 21 B1 20 B2 19 B3 18 B4 17 B5 16 B6 GND(1) GND 12 GND 13 15 B7 14 B8 74AVCH8T245 DIR VCC(A) DIR A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 24 VCC(B) 23 VCC(B) 22 OE 21 B1 20 B2 19 B3 18 B4 17 B5 16 B6 15 B7 14 B8 13 GND 001aai487 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 10 GND 11 A8 10 GND 11 GND 12 1 001aai488 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration TSSOP24 Fig 4. Pin configuration DHVQFN24 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 3 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 5.2 Pin description Table 2. Symbol VCC(A) DIR A1 to A8 GND[1] GND[1] GND[1] B1 to B8 OE VCC(B) VCC(B) [1] Pin description Pin 1 2 3, 4, 5, 6, 7, 8, 9, 10 11 12 13 22 23 24 Description supply voltage A (An, OE and DIR inputs are referenced to VCC(A)) direction control data input or output ground (0 V) ground (0 V) ground (0 V) output enable input (active LOW) supply voltage B (Bn inputs are referenced to VCC(B)) supply voltage B (Bn inputs are referenced to VCC(B)) 21, 20, 19, 18, 17, 16, 15, 14 data input or output All GND pins must be connected to ground (0 V). 6. Functional description Table 3. Function table[1] Input OE[2] L L H X DIR[2] L H X X Input/output[3] An[2] An = Bn input Z Z Bn input Bn = An Z Z Supply voltage VCC(A), VCC(B) 0.8 V to 3.6 V 0.8 V to 3.6 V 0.8 V to 3.6 V GND[3] [1] [2] [3] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. The An, DIR and OE input circuit is referenced to VCC(A); The Bn input circuit is referenced to VCC(B). If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC(A) VCC(B) IIK VI IOK VO IO ICC 74AVCH8T245_2 Parameter supply voltage A supply voltage B input clamping current input voltage output clamping current output voltage output current supply current Conditions Min −0.5 −0.5 Max +4.6 +4.6 +4.6 VCCO + 0.5 +4.6 ±50 100 Unit V V mA V mA V V mA mA VI < 0 V [1] −50 −0.5 −50 [1][2][3] [1] VO < 0 V Active mode Suspend or 3-state mode VO = 0 V to VCC ICC(A) or ICC(B) −0.5 −0.5 - © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 4 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol IGND Tstg Ptot [1] [2] [3] [4] Parameter ground current storage temperature total power dissipation Conditions Min −100 −65 Max +150 500 Unit mA °C mW Tamb = −40 °C to +125 °C [4] - The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 4.6 V. For TSSOP24 package: Ptot derates linearly at 5.5 mW/K above 60 °C. For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Symbol VCC(A) VCC(B) VI VO Tamb ∆t/∆V [1] [2] Recommended operating conditions Parameter supply voltage A supply voltage B input voltage output voltage ambient temperature input transition rise and fall rate VCCI = 0.8 V to 3.6 V [2] Conditions Min 0.8 0.8 0 Max 3.6 3.6 3.6 VCCO 3.6 +125 5 Unit V V V V V °C ns/V Active mode Suspend or 3-state mode [1] 0 0 −40 - VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. 9. Static characteristics Table 6. Typical static characteristics at Tamb = 25 °C[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH VOL II IBHL IBHH IBHLO IBHHO HIGH-level output voltage LOW-level output voltage input leakage current bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current Conditions VI = VIH or VIL IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V VI = VIH or VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V DIR, OE input; VI = 0 V or 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V A or B port; VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V A or B port; VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V A or B port; VCC(A) = VCC(B) = 1.2 V A or B port; VCC(A) = VCC(B) = 1.2 V [3] [4] [5] Min - Typ 0.69 0.07 Max - Unit V V ±0.025 ±0.25 µA 26 −24 27 −26 µA µA µA µA [6] 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 5 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state Table 6. Typical static characteristics at Tamb = 25 °C[1][2] …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOZ OFF-state output current Conditions A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V CI CI/O input capacitance input/output capacitance DIR, OE input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V A and B port; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V [7] Min - Typ ±0.5 ±0.5 ±0.5 ±0.1 ±0.1 1.5 4.3 Max ±2.5 ±2.5 ±2.5 ±1 ±1 - Unit µA µA µA µA µA pF pF [7] [7] [1] [2] [3] [4] [5] [6] [7] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the data input port. The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND and then raising it to VIL max. The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from LOW to HIGH. An external driver must sink at least IBHHO to switch this node from HIGH to LOW. For I/O ports, the parameter IOZ includes the input leakage current. Table 7. Static characteristics [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH Conditions −40 °C to +85 °C Min HIGH-level data input input voltage VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR, OE input VCC(A) = 0.8 V VCC(A) = 1.1 V to 1.95 V VCC(A) = 2.3 V to 2.7 V VCC(A) = 3.0 V to 3.6 V 0.70VCC(A) 0.65VCC(A) 1.6 2 0.70VCC(A) 0.65VCC(A) 1.6 2 V V V V 0.70VCCI 0.65VCCI 1.6 2 Max −40 °C to +125 °C Min 0.70VCCI 0.65VCCI 1.6 2 Max V V V V Unit 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 6 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL Conditions −40 °C to +85 °C Min LOW-level data input input voltage VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR, OE input VCC(A) = 0.8 V VCC(A) = 1.1 V to 1.95 V VCC(A) = 2.3 V to 2.7 V VCC(A) = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = −3 mA; VCC(A) = VCC(B) = 1.1 V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V II IBHL input leakage DIR, OE input; VI = 0 V or 3.6 V; current VCC(A) = VCC(B) = 0.8 V to 3.6 V bus hold LOW current A or B port VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V [3] −40 °C to +125 °C Min VCCO − 0.1 0.85 1.05 1.2 1.75 2.3 Max 0.30VCCI 0.35VCCI 0.7 0.8 Unit Max 0.30VCCI 0.35VCCI 0.7 0.8 0.30VCC(A) 0.35VCC(A) 0.7 0.8 - VCCO − 0.1 0.85 1.05 1.2 1.75 2.3 V V V V 0.30VCC(A) V 0.35VCC(A) V 0.7 0.8 V V V V V V V V - 0.1 0.25 0.35 0.45 0.55 0.7 ±1 - 0.1 0.25 0.35 0.45 0.55 0.7 ±5 V V V V V V µA 15 25 45 100 - 15 25 45 90 - µA µA µA µA 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 7 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHH Conditions [4] −40 °C to +85 °C Min Max ±5 ±5 −40 °C to +125 °C Min −15 −25 −45 −100 125 200 300 500 −125 −200 −300 −500 Max ±30 ±30 Unit bus hold A or B port HIGH current VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V −15 −25 −45 −100 [5] µA µA µA µA µA µA µA µA µA µA µA µA µA µA IBHLO bus hold LOW overdrive current A or B port VCC(A) = VCC(B) = 1.6 V VCC(A) = VCC(B) = 1.95 V VCC(A) = VCC(B) = 2.7 V VCC(A) = VCC(B) = 3.6 V 125 200 300 500 [6] IBHHO bus hold HIGH overdrive current A or B port VCC(A) = VCC(B) = 1.6 V VCC(A) = VCC(B) = 1.95 V VCC(A) = VCC(B) = 2.7 V VCC(A) = VCC(B) = 3.6 V −125 −200 −300 −500 [7] IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.6 V; VCC(B) = 0 V suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 3.6 V - [7] [7] - ±5 - ±30 µA IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V - ±5 ±5 - ±30 ±30 µA µA 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 8 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC supply current Conditions A port; VI = 0 V or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = 0 V or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI; VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V [1] [2] [3] [4] [5] [6] [7] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the data input port. The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND and then raising it to VIL max. The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from LOW to HIGH. An external driver must sink at least IBHHO to switch this node from HIGH to LOW. For I/O ports, the parameter IOZ includes the input leakage current. −40 °C to +85 °C Min −2 −2 Max 10 8 8 10 8 8 20 −40 °C to +125 °C Min −12 −12 Max 55 50 50 55 50 50 70 Unit µA µA µA µA µA µA µA µA µA - 16 - 65 µA Table 8. VCC(A) 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V Typical total supply current (ICC(A) + ICC(B)) VCC(B) 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 0.8 V 0.1 0.1 0.1 0.1 0.1 0.3 1.6 1.2 V 0.1 0.1 0.1 0.1 0.1 0.1 0.8 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.4 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.2 2.5 V 0.1 0.3 0.1 0.1 0.1 0.1 0.1 3.3 V 0.1 1.6 0.8 0.4 0.2 0.1 0.1 µA µA µA µA µA µA µA Unit 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 9 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 10. Dynamic characteristics Table 9. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter tpd tdis ten Conditions 0.8 V propagation delay An to Bn Bn to An disable time enable time OE to An OE to Bn OE to An OE to Bn [1] VCC(B) 1.2 V 7.0 12.4 16.2 10.0 21.9 11.1 1.5 V 6.2 12.1 16.2 9.0 21.9 9.8 1.8 V 6.0 11.9 16.2 9.1 21.9 9.4 2.5 V 5.9 11.8 16.2 8.7 21.9 9.4 3.3 V 6.0 11.8 16.2 9.3 21.9 9.6 14.4 14.4 16.2 17.6 21.9 22.2 Unit ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter tpd tdis ten Conditions 0.8 V propagation delay An to Bn Bn to An disable time enable time OE to An OE to Bn OE to An OE to Bn [1] VCC(A) 1.2 V 12.4 7.0 5.9 14.2 6.4 17.7 1.5 V 12.1 6.2 4.4 13.7 4.4 17.2 1.8 V 11.9 6.0 4.2 13.6 3.5 17.0 2.5 V 11.8 5.9 3.1 13.3 2.6 16.8 3.3 V 11.8 6.0 3.5 13.1 2.3 16.7 14.4 14.4 16.2 17.6 21.9 22.2 Unit ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 10 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter CPD power dissipation capacitance Conditions 0.8 V A port: (direction A to B); output enabled A port: (direction A to B); output disabled A port: (direction B to A); output enabled A port: (direction B to A); output disabled B port: (direction A to B); output enabled B port: (direction A to B); output disabled B port: (direction B to A); output enabled B port: (direction B to A); output disabled [1] VCC(A) = VCC(B) 1.2 V 0.2 0.2 9 0.6 9 0.6 0.2 0.2 1.5 V 0.2 0.2 10 0.6 10 0.6 0.2 0.2 1.8 V 0.3 0.3 10 0.7 10 0.7 0.3 0.3 2.5 V 0.4 0.4 11 0.7 11 0.7 0.4 0.4 3.3 V 0.5 0.5 13 0.8 13 0.8 0.5 0.5 0.2 0.2 9 0.6 9 0.6 0.2 0.2 Unit pF pF pF pF pF pF pF pF CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. [2] 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 11 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6. Symbol Parameter Conditions 1.2 V ± 0.1 V Min VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn VCC(A) = 1.4 V to 1.6 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn VCC(A) = 2.3 V to 2.7 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn VCC(A) = 3.0 V to 3.6 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn [1] VCC(B) 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V Min 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.0 1.1 0.5 0.5 0.5 0.5 0.5 1.1 0.5 0.5 0.5 0.5 0.5 1.1 Max 6.7 8.5 11.8 9.5 14.4 10.4 5.6 5.6 8.6 8.4 8.7 8.1 5.3 4.7 7.1 7.8 6.8 8.2 5.2 4.4 5.1 7.1 4.8 7.9 5.0 4.1 4.9 6.9 4.0 7.8 Min 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 5.8 8.3 11.8 9.4 14.4 9.0 4.7 5.3 8.6 7.6 8.7 7.1 4.5 4.5 7.1 6.9 6.8 6.7 4.3 3.8 5.1 6.3 4.8 6.4 4.1 3.5 4.9 6.0 4.0 6.2 Min 0.5 0.5 0.5 0.5 1.1 1.0 0.5 0.5 0.5 0.5 1.1 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 4.9 8.0 11.8 8.0 14.4 7.7 4.4 5.2 8.6 7.2 8.7 5.6 3.8 4.3 7.1 6.0 6.8 5.1 3.3 3.3 5.1 5.1 4.8 4.6 3.1 2.9 4.9 4.8 4.0 4.5 3.3 V ± 0.3 V Min 0.5 0.5 0.5 0.5 1.1 1.0 0.5 0.5 0.5 0.5 1.1 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 4.8 7.8 11.8 8.9 14.4 7.3 4.1 5.0 8.6 7.8 8.7 5.2 3.5 4.1 7.1 5.8 6.8 4.5 2.9 3.1 5.1 5.2 4.8 4.0 2.7 2.7 4.9 5.0 4.0 3.9 Max 9.0 9.0 11.8 12.3 14.4 14.2 8.5 6.7 8.6 11.2 8.7 12.8 8.3 5.8 7.1 10.9 6.8 12.4 8.0 4.9 5.1 10.4 4.8 11.9 7.8 4.8 4.9 10.1 4.0 11.7 Unit 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.0 1.1 0.5 0.5 0.5 0.5 0.5 1.1 0.5 0.5 0.5 0.5 0.5 1.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 12 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions 1.2 V ± 0.1 V Min VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn VCC(A) = 1.4 V to 1.6 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn VCC(A) = 2.3 V to 2.7 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn VCC(A) = 3.0 V to 3.6 V tpd tdis ten propagation delay disable time enable time An to Bn Bn to An OE to An OE to Bn OE to An OE to Bn [1] VCC(B) 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V Min 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.0 1.1 0.5 0.5 0.5 0.5 0.5 1.1 0.5 0.5 0.5 0.5 0.5 1.1 Max 7.4 9.4 13.0 10.5 15.9 11.5 6.2 6.2 9.5 9.3 9.6 9.0 5.9 5.2 7.9 8.6 7.5 9.1 5.8 4.9 5.7 7.9 5.3 8.7 5.5 4.6 5.4 7.6 4.4 8.6 Min 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.0 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 6.4 9.2 13.0 10.4 15.9 9.9 5.2 5.9 9.5 8.4 9.6 7.9 5.0 5.0 7.9 7.6 7.5 7.4 4.8 4.2 5.7 7.0 5.3 7.1 4.6 3.9 5.4 6.6 4.4 6.9 Min 0.5 0.5 0.5 0.5 1.1 1.0 0.5 0.5 0.5 0.5 1.1 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 5.4 8.8 13.0 8.8 15.9 8.5 4.9 5.8 9.5 8.0 9.6 6.2 4.2 4.8 7.9 6.6 7.5 5.7 3.7 3.7 5.7 5.7 5.3 5.1 3.5 3.2 5.4 5.3 4.4 5.0 3.3 V ± 0.3 V Min 0.5 0.5 0.5 0.5 1.1 1.0 0.5 0.5 0.5 0.5 1.1 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 5.3 8.6 13.0 9.8 15.9 8.1 4.6 5.5 9.5 8.6 9.6 5.8 3.9 4.6 7.9 6.4 7.5 5.0 3.2 3.5 5.7 5.8 5.3 4.4 3.0 3.0 5.4 5.5 4.4 4.3 Max 9.9 9.9 13.0 13.6 15.9 15.7 9.4 7.4 9.5 12.4 9.6 14.1 9.2 6.4 7.9 12.0 7.5 13.7 8.8 5.4 5.7 11.5 5.3 13.1 8.6 5.3 5.4 11.2 4.4 12.9 Unit 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.1 1.1 0.5 0.5 0.5 0.5 1.0 1.1 0.5 0.5 0.5 0.5 0.5 1.1 0.5 0.5 0.5 0.5 0.5 1.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 13 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 11. Waveforms VI An, Bn input GND tPHL VOH Bn, An output VOL VM 001aai475 VM tPLH Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. The data input (An, Bn) to output (Bn, An) propagation delay times VI OE input GND tPLZ VCCO output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aai474 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Table 14. Enable and disable times Measurement points Input[1] VM 0.5VCCI 0.5VCCI 0.5VCCI Output[2] VM 0.5VCCO 0.5VCCO 0.5VCCO VX VOL + 0.1 V VOL + 0.15 V VOL + 0.3 V VY VOH − 0.1 V VOH − 0.15 V VOH − 0.3 V Supply voltage VCC(A), VCC(B) 0.8 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 14 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 7. Table 15. Load circuit for switching times Test data Input VI[1] VCCI VCCI VCCI ∆t/∆V[2] ≤ 1.0 ns/V ≤ 1.0 ns/V ≤ 1.0 ns/V Load CL 15 pF 15 pF 15 pF RL 2 kΩ 2 kΩ 2 kΩ VEXT tPLH, tPHL open open open tPZH, tPHZ GND GND GND tPZL, tPLZ[3] 2VCCO 2VCCO 2VCCO Supply voltage VCC(A), VCC(B) 0.8 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] [3] VCCI is the supply voltage associated with the data input port. dV/dt ≥ 1.0 V/ns VCCO is the supply voltage associated with the output port. 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 15 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 12. Typical propagation delay characteristics 001aai476 001aai477 (1) (2) (3) (4) (5) (6) 24 tpd (ns) 20 21 tpd (ns) 17 (1) 16 12 (2) (3) (4) (5) (6) 13 8 4 0 20 40 CL (pF) 60 9 0 20 40 CL (pF) 60 a. Propagation delay (A to B); VCC(A) = 0.8 V (1) VCC(B) = 0.8 V. (2) VCC(B) = 1.2 V. (3) VCC(B) = 1.5 V. (4) VCC(B) = 1.8 V. (5) VCC(B) = 2.5 V. (6) VCC(B) = 3.3 V. b. Propagation delay (A to B); VCC(B) = 0.8 V (1) VCC(A) = 0.8 V. (2) VCC(A) = 1.2 V. (3) VCC(A) = 1.5 V. (4) VCC(A) = 1.8 V. (5) VCC(A) = 2.5 V. (6) VCC(A) = 3.3 V. Fig 8. Typical propagation delay vs load capacitance; Tamb = 25 °C 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 16 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 7 tPLH (ns) 5 001aai478 (1) 7 tPHL (ns) 001aai491 (1) (2) (3) (4) (5) 5 (2) (3) (4) (5) 3 3 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 a. LOW to HIGH propagation delay (A to B); VCC(A) = 1.2 V 7 tPLH (ns) 5 001aai479 (1) b. HIGH to LOW propagation delay (A to B); VCC(A) = 1.2 V 7 tPHL (ns) (1) 001aai480 (2) (3) (4) 5 (2) (3) 3 (5) 3 (4) (5) 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 c. LOW to HIGH propagation delay (A to B); VCC(A) = 1.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. d. HIGH to LOW propagation delay (A to B); VCC(A) = 1.5 V Fig 9. Typical propagation delay vs load capacitance; Tamb = 25 °C 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 17 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 7 tPLH (ns) 5 001aai481 7 tPHL (ns) 5 001aai482 (1) (1) (2) (3) (4) (2) (3) 3 (5) 3 (4) (5) 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 a. LOW to HIGH propagation delay (A to B); VCC(A) = 1.8 V 7 tPLH (ns) 5 (2) (3) (4) (5) b. HIGH to LOW propagation delay (A to B); VCC(A) = 1.8 V 7 tPHL (ns) 5 (1) 001aai483 001aai486 (1) (2) (3) 3 3 (4) (5) 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 c. LOW to HIGH propagation delay (A to B); VCC(A) = 2.5 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. d. HIGH to LOW propagation delay (A to B); VCC(A) = 2.5 V Fig 10. Typical propagation delay vs load capacitance; Tamb = 25 °C 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 18 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 7 tPLH (ns) 5 001aai485 7 tPHL (ns) 5 001aai484 (1) (1) (2) (2) (3) (3) 3 (4) (5) 3 (4) (5) 1 0 20 40 CL (pF) 60 1 0 20 40 CL (pF) 60 a. LOW to HIGH propagation delay (A to B); VCC(A) = 3.3 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. b. HIGH to LOW propagation delay (A to B); VCC(A) = 3.3 V Fig 11. Typical propagation delay vs load capacitance; Tamb = 25 °C 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 19 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 13. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 12 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT355-1 (TSSOP24) 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 20 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm SOT815-1 D B A E A A1 c detail X terminal 1 index area C terminal 1 index area 2 L 12 e1 e b 11 vMCAB wM C y1 C y 1 Eh e2 24 13 23 Dh 0 14 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.6 5.4 Dh 4.25 3.95 E (1) 3.6 3.4 Eh 2.25 1.95 e 0.5 e1 4.5 e2 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT815-1 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION ISSUE DATE 03-04-29 Fig 13. Package outline SOT815-1 (DHVQFN24) 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 21 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 14. Abbreviations Table 16. Acronym CDM CMOS DUT ESD HBM MM Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 17. Revision history Release date 20090428 Data sheet status Product data sheet Change notice Supersedes 74AVCH8T245_1 Document ID 74AVCH8T245_2 Modifications: 74AVCH8T245_1 • Section 5 “Pinning information”: Changed: pin names changed in pin description table. Product data sheet - 20080709 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 22 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AVCH8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 23 of 24 NXP Semiconductors 74AVCH8T245 8-bit dual supply translating transceiver; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical propagation delay characteristics. . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 April 2009 Document identifier: 74AVCH8T245_2