INTEGRATED CIRCUITS
74AVCM162836
20-bit registered driver with inverted
register enable and 15 Ω termination
resistors (3-State)
Product specification
File under Integrated Circuits ICL03
2001 Apr 20
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
FEATURES
74AVCM162836
PIN CONFIGURATION
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7.
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• Low inductance multiple VCC and GND pins for minimum noise
CP
OE
1
56
Y0
2
55
A0
Y1
3
54
A1
GND
4
53
GND
Y2
5
52
A2
Y3
6
51
A3
VCC
7
50
VCC
Y4
8
49
A4
Y5
9
48
A5
Y6
10
47
A6
GND
11
46
GND
Y7
12
45
A7
DESCRIPTION
Y8
13
44
A8
The 74AVCM162836 is a 20-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
Y9
14
43
A9
Y10
15
42
A10
Y11
16
41
A11
Y12
17
40
A12
GND
18
39
GND
Y13
19
38
A13
Y14
20
37
A14
and ground bounce
• Integrated 15 Ω termination resistors to minimize output overshoot
and undershoot
• Full PC133 solution provided when used with PCK2510S and
CBT16292
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor (Live
Insertion).
Y15
21
36
A15
VCC
22
35
VCC
Y16
23
34
A16
Y17
24
33
A17
GND
25
32
GND
Y18
26
31
A18
Y19
27
30
A19
NC
28
29
LE
SH00159
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns; CL = 30 pF.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
An to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
tPHL/tPLH
Propagation delay
LE to Yn;
CP to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
CI
Input capacitance
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
TYPICAL
UNIT
2.6
2.0
1.7
ns
3.0
2.4
2.0
ns
5.0
pF
Outputs enabled
25
Output disabled
6
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
2001 Apr 20
2
TEMPERATURE
RANGE
ORDER CODE
DRAWING
NUMBER
–40°C to +85°C
74AVCM162836DGG
SOT364-1
853-2175 26096
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
PIN DESCRIPTION
LOGIC SYMBOL (IEEE/IEC)
PIN NUMBER
SYMBOL
28
NC
NAME AND FUNCTION
No connection
2, 3, 5, 6, 8, 9, 10, 12,
13, 14, 15, 16, 17, 19,
20, 21, 23, 24, 26, 27
Y0 to Y19
4, 11, 18, 25, 32, 35, 39,
46, 53
GND
7, 22, 35, 50
VCC
Positive supply voltage
OE
1
29
CP
55, 54, 52, 51, 49, 48,
47, 45, 44, 43, 42, 41,
40, 38, 37, 36, 34, 33,
31, 30
Data outputs
OE
1
CP
56
LE
29
EN1
2C3
C3
G2
LE
56
74AVCM162836
A0 to A19
Y0
2
55
Y1
3
54
Y2
5
52
Output enable input
(active LOW)
Y3
6
Y4
8
49
Latch enable input
(active LOW)
Y5
9
48
Y6
10
47
Clock input
Y7
12
45
Y8
13
44
Y9
14
43
Y10
15
42
Y11
16
41
Y12
17
40
Y13
19
38
Y14
20
37
Y15
21
36
Y16
23
34
Y17
24
33
26
31
27
30
Ground (0V)
Data inputs
LOGIC SYMBOL
OE
CP
Y18
Y19
1∇
1
51
3D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
LE
A0
SH00160
D
LE
Y0
FUNCTION TABLE
CP
INPUTS
TO THE 19 OTHER CHANNELS
SH00163
H
L
X
Z
↑
OUTPUTS
OE
LE
CP
A
H
X
X
X
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
L
H
H
X
Y01
L
H
L
X
Y02
=
=
=
=
=
Z
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
2001 Apr 20
3
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
74AVCM162836
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
168-pin SDR SDRAM DIMM
SDRAM
BACK SIDE
FRONT SIDE
74AVCM162836
74AVCM162836
74AVCM162836
PCK2509S or PCK2510S
The PLL clock distribution device and AVCM registered drivers reduce signal loads on the memory
controller and prevent timing delays and waveform distortions that would cause unreliable operation
SW00423
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
VI
VO
Tamb
tr, tf
PARAMETER
CONDITIONS
MIN
MAX
UNIT
DC supply voltage
(according to JEDEC Low Voltage Standards)
1.65
2.3
3.0
1.95
2.7
3.6
V
DC supply voltage
(for low voltage applications)
1.2
3.6
DC Input voltage range
0
3.6
DC output voltage range; output 3-State
0
3.6
DC output voltage range;
output HIGH or LOW state
0
VCC
–40
+85
°C
0
0
0
30
20
10
ns/V
Operating free-air temperature range
VCC = 1.65 to 2.3 V
VCC = 2.3 to 3.0 V
VCC = 3.0 to 3.6 V
Input rise and fall times
V
V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V)
SYMBOL
VCC
PARAMETER
CONDITIONS
DC supply voltage
RATING
UNIT
–0.5 to +4.6
V
–50
mA
–0.5 to 4.6
V
"50
mA
–0.5 to 4.6
V
IIK
DC input diode current
VI t0
VI
DC input voltage
For all inputs1
IOK
DC output diode current
VO uVCC or VO t 0
VO
DC output voltage; output 3-State
Note 1
VO
DC output voltage;
output HIGH or LOW state
Note 1
–0.5 to VCC +0.5
V
IO
DC output source or sink current
VO = 0 to VCC
IGND, ICC
Tstg
PTOT
DC VCC or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125 °C
above +55 °C derate linearly with 8 mW/K
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2001 Apr 20
4
"50
mA
"100
mA
–65 to +150
°C
600
mW
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
74AVCM162836
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
VCC = 1.2 V
VIH
HIGH level Input voltage
UNIT
TYP1
MAX
VCC
–
–
0.65VCC
0.9
–
VCC = 2.3 to 2.7 V
1.7
1.2
–
VCC = 3.0 to 3.6 V
VCC = 1.65 to 1.95 V
V
2.0
1.5
–
VCC = 1.2 V
–
–
GND
VCC = 1.65 to 1.95 V
–
0.9
0.35VCC
VCC = 2.3 to 2.7 V
–
1.2
0.7
VCC = 3.0 to 3.6 V
–
1.5
0.8
VCC = 1.65 to 3.6 V; VI = VIH or VIL;
IO = –100 µA
0 20
VCC0.20
VCC
–
VCC = 1.65 V; VI = VIH or VIL; IO = –4 mA
VCC0.45
VCC0.10
–
VCC = 2.3 V; VI = VIH or VIL; IO = –8 mA
VCC0.55
VCC0.28
–
VCC = 3.0 V; VI = VIH or VIL; IO = –12 mA
VCC0.70
VCC0.32
–
VCC = 1.65 to 3.6 V; VI = VIH or VIL;
IO = 100 µA
–
GND
0 20
0.20
VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA
–
0.10
0.45
VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA
–
0.26
0.55
VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA
–
0.36
0.70
Input
In
ut leakage current
VCC = 1.65
1 65 to 3.6
3 6 V;
VI = VCC or GND
–
0.1
2.5
IOFF
3-State output OFF-state current
VCC = 0 V; VI or VO = 3.6 V
–
0.1
10
µA
IIHZ/IILZ
3-State output OFF-state current
VCC = 1.65 to 3.6 V; VI = VCC or GND
–
0.1
12.5
µA
VCC = 1.65 to 2.7 V; VI = VIH or VIL;
VO = VCC or GND
–
0.1
5
VCC = 3.0 to 3.6 V; VI = VIH or VIL;
VO = VCC or GND
–
0.1
10
VCC = 1.65 to 2.7 V; VI = VCC or GND; IO = 0
–
0.1
20
VCC = 3.0 to 3.6 V; VI = VCC or GND; IO = 0
–
0.2
40
VIL
VOH
VOL
II
IOZ
O
ICC
LOW level Input voltage
HIGH level output voltage
g
LOW level output voltage
g
3 State output OFF-state
3-State
OFF state current
Quiescent supply current
NOTE:
1. All typical values are at Tamb = 25 °C.
2001 Apr 20
5
V
V
V
µA
µA
µA
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
74AVCM162836
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3 ± 0.3 V
VCC = 2.5 ± 0.2 V
VCC = 1.8 ± 0.15 V
VCC = 1.2 V
UNIT
MIN
TYP1
MAX
MIN
TYP1
MAX
MIN
TYP1
MAX
MIN
TYP
Propagation delay An to Yn
1, 7
0.7
1.7
2.5
0.8
2.0
3.1
1.0
2.6
4.5
–
5.2
Propagation delay LE to Yn
2, 7
0.7
2.0
2.7
0.8
2.4
3.3
1.0
3.0
5.0
–
5.6
Propagation delay CP to Yn
3, 7
0.7
1.9
2.5
0.8
2.2
3.0
1.0
2.8
4.5
–
5.2
tPZH/tPZL
3-State output enable time OE
to Yn
6, 7
1.0
2.5
4.5
1.0
2.8
4.5
1.5
3.5
6.5
–
5.5
ns
tPHZ/tPLZ
3-State output disable time OE
to Yn
6, 7
1.0
2.5
3.5
1.0
2.4
4.0
1.5
4.0
6.5
–
6.9
ns
CP pulse width HIGH or LOW
3, 7
1.0
–
–
1.2
–
–
2.0
–
–
–
–
LE pulse width HIGH
2, 7
1.0
–
–
1.2
–
–
2.0
–
–
–
–
Set-up time An to CP
5, 7
0.7
–
–
0.7
–
–
0.7
–
–
1.0
–
Set-up time An to LE HIGH
4, 7
0.5
–
–
0.5
–
–
0.5
–
–
0.2
–
Set-up time An to LE LOW
4, 7
0.5
–
–
0.5
–
–
0.6
–
–
2.0
–
Hold time An to CP
5, 7
0.9
–
–
0.9
–
–
1.0
–
–
1.5
–
Hold time An to LE HIGH
4, 7
1.6
–
–
1.7
–
–
2.0
–
–
3.2
–
Hold time An to LE LOW
4, 7
1.4
–
–
1.5
–
–
1.7
–
–
2.8
–
ns
Maximum clock pulse frequency
3, 7
500
–
–
400
–
–
250
–
–
–
–
MHz
tPHL/tPLH
tW
ns
ns
ns
tSU
ns
ns
th
Fmax
NOTES:
1. All typical values are measured at Tamb = 25 °C and at VCC = 1.8 V, 2.5 V, 3.3 V.
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE
VM = 0.5 VCC
VX = VOL + 0.300 V
VY = VOH – 0.300 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
VI
LE INPUT
GND
NOTE: VM = 0.5 VCC at VCC = 2.3 to 2.7 V
SH00165
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
VM
GND
tPLH
VOH
VM
VOL
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00132
Waveform 1. Input (An) to output (Yn) propagation delay
2001 Apr 20
VM
VOL
VI
Yn
OUTPUT
tPLH
VOH
Yn OUTPUT
VM = 0.5 VCC
VX = VOL + 0.15 V
VY = VOH – 0.15 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
tPHL
VM
tW
tPHL
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND
VCC < 2.3 V RANGE
An
INPUT
VM
6
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
74AVCM162836
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE
(Continued)
VM = 0.5 VCC
VX = VOL + 0.300V
VY = VOH – 0.300V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
VI
GND
VI
An INPUT
GND
VOH
VM
Yn OUTPUT
VOL
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00136
1/fMAX
VI
Waveform 5. Data set-up and hold times for the An input to
the clock CP input
VM
tW
GND
tPHL
tPLH
VI
VOH
VM
Yn OUTPUT
nOE INPUT
VOL
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
VM
GND
SH00135
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
tPLZ
tPZL
VCC
ÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉ
OUTPUT
LOW-to-OFF
OFF-to-LOW
VI
An
INPUT
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
th
th
VM = 0.5 VCC
VX = VOL + 0.15V
VY = VOH – 0.15V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
VM
tsu
tsu
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND
VCC < 2.3V RANGE (Continued)
CP INPUT
VM
CP INPUT
VM
VX
VM
VOL
GND
th
tSU
tPHZ
th
tSU
VI
LE
INPUT
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
VM
GND
VY
VM
GND
outputs
enabled
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00166
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
outputs
disabled
outputs
enabled
SH00137
Waveform 6. 3-State enable and disable times
Waveform 4. Data set-up and hold times for the An input to the
LE input
2001 Apr 20
tPZH
VOH
7
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
TEST CIRCUIT
S1
VCC
RL
VO
VI
PULSE
GENERATOR
2 * VCC
Open
GND
D.U.T.
RT
RL
CL
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
VCC
GND
VCC
VI
RL
< 2.3 V
VCC
1000 Ω
2.3–2.7 V
VCC
500 Ω
3.0 –3.6 V
VCC
500 Ω
SV01883
Waveform 7. Load circuitry for switching times
2001 Apr 20
8
74AVCM162836
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
2001 Apr 20
9
74AVCM162836
SOT364-1
Philips Semiconductors
Product specification
20-bit registered driver with inverted register enable
and 15 Ω termination resistors (3-State)
74AVCM162836
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Copyright Philips Electronics North America Corporation 2001
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 04-01
Document order number:
Philips
Semiconductors
2001 Apr 20
10
9397-750-08281
工商网监
湘ICP备2023018690号
