74AXP1G02GMH

74AXP1G02 Low-power 2-input NOR gate Rev. 2 — 9 July 2021 Product data sheet 1. General description The 74AXP1G02 is a single 2-input NOR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • • • Wide supply voltage range from 0.7 V to 2.75 V Low input capacitance; CI = 0.5 pF (typical) Low output capacitance; CO = 1.0 pF (typical) Low dynamic power consumption; CPD = 2.6 pF at VCC = 1.2 V (typical) Low static power consumption; ICC = 0.6 μA (85 °C maximum) High noise immunity Complies with JEDEC standard: • JESD8-12A.01 (1.1 V to 1.3 V) • JESD8-11A.01 (1.4 V to 1.6 V) • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A.01 (2.3 V to 2.7 V) ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV • CDM JESD22-C101E exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 2.75 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 °C to +85 °C 74AXP1G02 Nexperia Low-power 2-input NOR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AXP1G02GM -40 °C to +85 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74AXP1G02GN -40 °C to +85 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm SOT1115 74AXP1G02GS -40 °C to +85 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm SOT1202 74AXP1G02GX -40 °C to +85 °C X2SON5 plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 × 0.8 × 0.32 mm SOT1226-3 4. Marking Table 2. Marking Type number Marking code[1] 74AXP1G02GM rB 74AXP1G02GN rB 74AXP1G02GS rB 74AXP1G02GX rB [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 B 2 A Y 1 4 2 Logic symbol 74AXP1G02 Product data sheet ≥1 4 mna104 mna103 Fig. 1. B Fig. 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 Y A Fig. 3. mna105 Logic diagram © Nexperia B.V. 2021. All rights reserved 2 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate 6. Pinning information 6.1. Pinning 74AXP1G02 B 1 6 VCC A 2 5 n.c. GND 3 4 74AXP1G02 B 1 VCC 4 Y 3 GND Y 2 A aaa-014645 Transparent top view Fig. 4. 5 aaa-014646 Pin configuration SOT886, SOT1115 and SOT1202 (XSON6) Transparent top view Fig. 5. Pin configuration SOT1226-3 (X2SON5) 6.2. Pin description Table 3. Pin description Symbol Pin Description X2SON5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Output Input A B Y L L H L H L H L L H H L 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 3 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO output current ICC Min Max Unit -0.5 +3.3 V -50 - -0.5 +3.3 -50 - -0.5 +3.3 V - ±20 mA supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] Conditions VI < 0 V [1] VO < 0 V [1] VO = 0 V to VCC Tamb = -40 °C to +85 °C [2] mA V mA The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT1115 (XSON6) package: Ptot derates linearly with 3.2 mW/K above 71 °C. For SOT1202 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT1226-3 (X2SON5) package: Ptot derates linearly with 3.0 mW/K above 67 °C. 9. Recommended operating conditions Table 6. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Tamb ambient temperature Δt/ΔV input transition rise and fall rate 74AXP1G02 Product data sheet Min Max Unit 0.7 2.75 V 0 2.75 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 2.75 V -40 +85 °C 0 200 ns/V VCC = 0.7 V to 2.75 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 4 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions, unless otherwise specified; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage VOH HIGH-level output voltage Conditions Tamb = 25 °C Min Typ Max Min Max VCC = 0.75 V to 0.85 V 0.75VCC - - 0.75VCC - V VCC = 1.1 V to 1.95 V 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.6 - - 1.6 - V VCC = 0.75 V to 0.85 V - - 0.25VCC - 0.25VCC V VCC = 1.1 V to 1.95 V - - 0.35VCC - 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V IO = -20 μA; VCC = 0.7 V - 0.69 - - - V IO = -100 μA; VCC = 0.75 V 0.65 - - 0.65 - V IO = -2 mA; VCC = 1.1 V 0.825 - - 0.825 - V IO = -3 mA; VCC = 1.4 V 1.05 - - 1.05 - V IO = -4.5 mA; VCC = 1.65 V 1.2 - - 1.2 - V IO = -8 mA; VCC = 2.3 V 1.7 - - 1.7 - V - 0.01 - - - V - - 0.1 - 0.1 V IO = 2 mA; VCC = 1.1 V - - 0.275 - 0.275 V IO = 3 mA; VCC = 1.4 V - - 0.35 - 0.35 V IO = 4.5 mA; VCC = 1.65 V - - 0.45 - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.7 - 0.7 V LOW-level output IO = 20 μA; VCC = 0.7 V voltage IO = 100 μA; VCC = 0.75 V VOL Tamb = -40 °C to +85 °C Unit II input leakage current VI = 0 V to 2.75 V; VCC = 0 V to 2.75 V [1] - 0.001 ±0.1 - ±0.5 μA IOFF power-off leakage current VI or VO = 0 V to 2.75 V; VCC = 0 V [1] - 0.01 ±0.1 - ±0.5 μA ΔIOFF additional power- VI or VO = 0 V or 2.75 V; off leakage VCC = 0 V to 0.1 V current [1] - 0.02 ±0.1 - ±0.5 μA ICC supply current [1] - 0.01 0.3 - 0.6 μA ΔICC additional supply VI = VCC - 0.5 V; IO = 0 A; current VCC = 2.5 V - 2 100 - 150 μA [1] VI = 0 V or VCC; IO = 0 A Typical values are measured at VCC = 1.2 V. 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 5 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 12. Symbol Parameter tpd propagation delay Conditions Tamb = 25 °C Tamb = -40 °C to +85 °C Unit Min Typ[1] Max Min Max 2 11 32 1 98 ns VCC = 1.1 V to 1.3 V 1.9 4.3 6.7 1.7 7.0 ns VCC = 1.4 V to 1.6 V 1.5 3.3 5.1 1.3 5.3 ns VCC = 1.65 V to 1.95 V 1.3 2.6 3.8 1.1 4.0 ns 1.1 2.0 2.8 0.9 3.0 ns - - - 1.0 - ns A, B to Y; see Fig. 6 [2] [3] VCC = 0.75 V to 0.85 V VCC = 2.3 V to 2.7 V tt transition time VCC = 2.7 V; see Fig. 6 [4] CI input capacitance VI = 0 V or VCC; VCC = 0 V to 2.75 V - 0.5 - - - pF CO output capacitance - 1.0 - - - pF CPD power dissipation fi = 1 MHz; VI = 0 V to VCC capacitance V = 0.75 V to 0.85 V - 2.4 - - - pF VCC = 1.1 V to 1.3 V - 2.4 - - - pF VCC = 1.4 V to 1.6 V - 2.5 - - - pF VCC = 1.65 V to 1.95 V - 2.5 - - - pF VCC = 2.3 V to 2.7 V - 2.8 - - - pF VO = 0 V; VCC = 0 V CC [1] [2] [3] [4] [5] [5] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL. For additional propagation delay values at different load capacitances, see Fig. 7 to Fig. 11. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi × N + CL x VCC x fo where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching. 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 6 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate 11.1. Waveforms, graphs and test circuit VI A, B input VM VM GND tPLH VOH tPHL 90 % Y output 90 % VM VOL VM 10 % 10 % tTLH tTHL aaa-014647 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. The data input (A, B) to output (Y) propagation delays Table 9. Measurement points Supply voltage Input Output VCC VM VI tr = tf VM 0.75 V to 2.7 V 0.5VCC VCC ≤ 3.0 ns 0.5VCC aaa-008211 8 t (ns) aaa-008212 10 (3) (3) t (ns) 8 6 (2) (1) 4 (2) 6 (1) 4 2 0 2 0 20 40 60 80 100 0 120 140 CL (pF) Tamb = -40 °C to +85 °C unless otherwise specified. (1) Minimum: VCC = 2.7 V (2) Typical: Tamb = 25 °C; VCC = 2.5 V (3) Maximum: VCC = 2.3 V Fig. 7. Additional tpd versus load capacitance 74AXP1G02 Product data sheet 0 20 40 60 80 100 120 140 CL (pF) Tamb = -40 °C to +85 °C unless otherwise specified. (1) Minimum: VCC = 1.95 V (2) Typical: Tamb = 25 °C; VCC = 1.8 V (3) Maximum: VCC = 1.65 V Fig. 8. Additional tpd versus load capacitance All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 7 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate aaa-008213 (3) 12 t (ns) 10 aaa-008214 20 t (ns) (3) 16 8 (2) 12 6 (2) (1) 8 4 (1) 4 2 0 0 20 40 60 80 100 0 120 140 CL (pF) Tamb = -40 °C to +85 °C unless otherwise specified. (1) Minimum: VCC = 1.6 V (2) Typical: Tamb = 25 °C; VCC = 1.5 V (3) Maximum: VCC = 1.4 V Fig. 9. Additional tpd versus load capacitance 0 20 40 60 80 100 120 140 CL (pF) Tamb = -40 °C to +85 °C unless otherwise specified. (1) Minimum: VCC = 1.3 V (2) Typical: Tamb = 25 °C; VCC = 1.2 V (3) Maximum: VCC = 1.1 V Fig. 10. Additional tpd versus load capacitance aaa-008215 32 (3) t (ns) 24 16 8 (2) (1) 0 0 5 10 15 20 25 30 35 CL (pF) Tamb = -40 °C to +85 °C unless otherwise specified. (1) Minimum: VCC = 0.85 V (2) Typical: Tamb = 25 °C; VCC = 0.8 V (3) Maximum: VCC = 0.75 V Fig. 11. Additional tpd versus load capacitance 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 8 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 12. Test circuit for measuring switching times Table 10. Test data Supply voltage Load VEXT VCC CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.75 V to 2.7 V 5 pF 10 kΩ 0V 0V 2 × VCC 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 9 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate 12. Package outline SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig. 13. Package outline SOT886 (XSON6) 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 10 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 e1 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig. 14. Package outline SOT1115 (XSON6) 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 11 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig. 15. Package outline SOT1202 (XSON6) 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 12 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0.8 x 0.32 mm SOT1226-3 C Seating Plane X 5x y C D A B E A A3 pin 1 index area A1 pin 1 index area e 1 2 b (4x) v w y1 C C A B C L (4x) 3 k D h (6x) x) (4 5 4 0 1 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 A3 D Dh E b e K L max 0.35 0.04 0.85 0.30 0.85 0.25 0.27 0.10 0.80 0.25 0.80 0.20 0.50 0.22 nom 0.32 0.02 (Typ.) min 0.30 0.00 0.75 0.20 0.75 0.15 0.20 0.17 v 0.1 w y y1 0.05 0.05 0.05 sot1226-3_po Outline version SOT1226-3 References IEC JEDEC EIAJ European projection Issue date 19-11-06 19-11-07 --- Fig. 16. Package outline SOT1226-3 (X2SON5) 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 13 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AXP1G02 v.2 20210709 Product data sheet - 74AXP1G02 v.1 Modifications: • • 74AXP1G02 v.1 20140825 74AXP1G02 Product data sheet SOT1226 (X2SON5) package changed to SOT1226-3 (X2SON5) package. Table 5: Derating values for Ptot total power dissipation updated. Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 - © Nexperia B.V. 2021. All rights reserved 14 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 15 / 16 74AXP1G02 Nexperia Low-power 2-input NOR gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveforms, graphs and test circuit............................7 12. Package outline........................................................ 10 13. Abbreviations............................................................ 14 14. Revision history........................................................14 15. Legal information......................................................15 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 9 July 2021 74AXP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 July 2021 © Nexperia B.V. 2021. All rights reserved 16 / 16