74HC02BQ

74HC02; 74HCT02 Quad 2-input NOR gate Rev. 03 — 18 September 2008 Product data sheet 1. General description The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC02; 74HCT02 provides a quad 2-input NOR function. 2. Features I Input levels: N For 74HC02: CMOS level N For 74HCT02: TTL level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74HC02N 74HCT02N 74HC02D 74HCT02D 74HC02DB 74HCT02DB 74HC02PW 74HCT02PW 74HC02BQ 74HCT02BQ −40 °C to +125 °C DHVQFN14 −40 °C to +125 °C TSSOP14 −40 °C to +125 °C SSOP14 −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT108-1 SOT337-1 SOT402-1 −40 °C to +125 °C Name DIP14 Description plastic dual in-line package; 14 leads (300 mil) Version SOT27-1 Type number plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate 4. Functional diagram 2 1Y 1 3 5 2Y 4 6 8 9 4Y 13 11 12 mna216 2 3 5 6 8 9 11 12 1A 1B 2A 2B 3A 3B 4A 4B ≥1 1 ≥1 4 3Y 10 ≥1 10 A Y B mna215 ≥1 13 001aah084 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning terminal 1 index area 1A 1Y 1A 1B 2Y 2A 2B GND 1 2 3 4 5 6 7 001aac919 2 3 4 5 6 7 GND 3A 8 14 VCC 13 4Y 12 4B 11 4A 10 3Y 9 3B 14 VCC 13 4Y 12 4B 1B 2Y 2A 2B GND(1) 02 11 4A 10 3Y 9 8 3B 3A 1 1Y 02 001aac920 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Symbol 1Y to 4Y 1A to 4A 1B to 4B GND VCC Pin description Pin 1, 4, 10, 13 2, 5, 8, 11 3, 6, 9,12 7 14 Description data output data input data input ground (0 V) supply voltage 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 2 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate 6. Functional description Table 3. Input nA L X H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. Function table[1] Output nB L H X nY H L L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP14 package SO14, (T)SSOP14 and DHVQFN14 packages [1] [2] [2] Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V −0.5 V < VO < VCC + 0.5 V [1] [1] Min −0.5 −50 −65 - Max +7 ±20 ±20 ±25 50 +150 750 500 Unit V mA mA mA mA mA °C mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC VI VO Tamb 74HC_HCT02_3 Conditions Min 2.0 0 0 −40 74HC02 Typ 5.0 Max 6.0 VCC VCC +125 Min 4.5 0 0 −40 74HCT02 Typ 5.0 Max 5.5 VCC VCC +125 Unit V V V °C supply voltage input voltage output voltage ambient temperature © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 3 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate Table 5. Recommended operating conditions …continued Voltages are referenced to GND (ground = 0 V) …continued Symbol Parameter ∆t/∆V input transition rise and fall rate Conditions Min VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 74HC02 Typ 1.67 Max 625 139 83 Min 74HCT02 Typ 1.67 Max 139 ns/V ns/V ns/V Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC02 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI input leakage current supply current input capacitance VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0 0 0 0.15 0.16 3.5 0.1 0.1 0.1 0.26 0.26 ±0.1 2.0 0.1 0.1 0.1 0.33 0.33 ±1 20 0.1 0.1 0.1 0.4 0.4 ±1 40 V V V V V µA µA pF 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 1.9 4.4 5.9 3.84 5.34 1.9 4.4 5.9 3.7 5.2 V V V V V 1.5 3.15 4.2 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 4 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HCT02 VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL; VCC = 4.5 V IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 µA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC ∆ICC input leakage current supply current additional supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V per input pin; VI = VCC − 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V 0 0.15 150 0.1 0.26 ±0.1 2.0 540 0.1 0.33 ±1 20 675 0.1 0.4 ±1 40 735 V V µA µA µA 4.4 3.98 4.5 4.32 4.4 3.84 4.4 3.7 V V 2.0 1.6 1.2 0.8 2.0 0.8 2.0 0.8 V V Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter Conditions Min 74HC02 tpd propagation delay nA, nB to nY; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tt transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance per package; VI = GND to VCC [3] [2] [1] 25 °C Typ Max −40 °C to +125 °C Unit Max (85 °C) Max (125 °C) - 25 9 7 7 19 7 6 22 90 18 15 75 15 13 - 115 23 20 95 19 16 - 135 27 23 110 22 19 - ns ns ns ns ns ns ns pF 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 5 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter Conditions Min 74HCT02 tpd propagation delay nA, nB to nY; see Figure 6 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt CPD transition time power dissipation capacitance VCC = 4.5 V; see Figure 6 per package; VI = GND to VCC − 1.5 V [2] [3] [1] 25 °C Typ Max −40 °C to +125 °C Unit Max (85 °C) Max (125 °C) - 11 9 7 24 19 15 - 24 19 - 29 22 - ns ns ns pF [1] [2] [3] tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑ (CL × VCC2 × fo) = sum of outputs. 11. Waveforms VI nA, nB input GND tPHL VOH nY output VOL tTHL VY VM VX tTLH 001aai814 VM tPLH Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. Type 74HC02 74HCT02 Input to output propagation delays Measurement points Input VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V VX 0.1VCC 0.1VCC VY 0.9VCC 0.9VCC 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 6 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate VI negative pulse GND tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VCC G VI VO VM VI positive pulse GND VM DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Table 9. Type 74HC02 74HCT02 Load circuitry for measuring switching times Test data Input VI VCC 3.0 V tr, tf 6.0 ns 6.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF tPLH, tPHL tPLH, tPHL Test 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 7 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D seating plane ME A2 A L A1 c Z e b1 b 14 8 MH wM (e 1) pin 1 index E 1 7 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 8. Package outline SOT27-1 (DIP14) 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 8 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT108-1 (SO14) 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 9 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE vM A Z 14 8 Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT337-1 (SSOP14) 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 10 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 11. Package outline SOT402-1 (TSSOP14) 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 11 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 12 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM LSTTL MM TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20080918 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT02_CNV_2 Document ID 74HC_HCT02_3 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type numbers 74HC02BQ and 74HCT02BQ (DHVQFN14 package) Product specification - 74HC_HCT02_CNV_2 19970827 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 13 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 September 2008 14 of 15 NXP Semiconductors 74HC02; 74HCT02 Quad 2-input NOR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 September 2008 Document identifier: 74HC_HCT02_3