74HC08; 74HCT08
Quad 2-input AND gate
Rev. 5 — 30 November 2015
Product data sheet
1. General description
The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC08: CMOS level
For 74HCT08: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
74HC08D
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
40 C to +125 C
DHVQFN14
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
74HCT08D
74HC08DB
74HCT08DB
74HC08PW
74HCT08PW
74HC08BQ
74HCT08BQ
74HC08; 74HCT08
NXP Semiconductors
Quad 2-input AND gate
4. Functional diagram
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Fig 1.
PQD
PQD
PQD
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
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+&7
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+&7
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DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and (T)SSOP14
74HC_HCT08
Product data sheet
Fig 5.
Pin configuration DHVQFN14
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 15
74HC08; 74HCT08
NXP Semiconductors
Quad 2-input AND gate
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A to 4A
1, 4, 9, 12
data input
1B to 4B
2, 5, 10,13
data input
1Y to 4Y
3, 6, 8, 11
data output
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
Output
nA
nB
L
L
L
L
H
L
H
L
L
H
H
H
[1]
nY
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
IO
output current
0.5 V < VO < VCC + 0.5 V
ICC
supply current
IGND
ground current
Tstg
storage temperature
total power dissipation
Ptot
Conditions
SO14, (T)SSOP14 and DHVQFN14
packages
Min
Max
0.5
+7
V
[1]
-
20
mA
[1]
-
20
mA
-
25
mA
-
50
mA
50
-
mA
65
+150
C
-
500
mW
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
Unit
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 15
74HC08; 74HCT08
NXP Semiconductors
Quad 2-input AND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC08
Min
Typ
74HCT08
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
-
+125
40
-
+125
C
t/V
input transition rise and fall rate
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4.0 mA; VCC = 4.5 V
3.98
4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
5.34
-
5.2
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
74HC08
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VI = VIH or VIL
VI = VIH or VIL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
0.1
-
1
-
1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
2.0
-
20
-
40
A
74HC_HCT08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 15
74HC08; 74HCT08
NXP Semiconductors
Quad 2-input AND gate
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
CI
25 C
Conditions
input
capacitance
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
3.5
-
-
-
-
-
pF
74HCT08
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA
3.98
4.32
-
3.84
-
3.7
-
V
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
0
0.1
-
0.1
-
0.1
V
IO = 5.2 mA
-
0.15
0.26
-
0.33
-
0.4
V
VOL
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
-
0.1
-
1
-
1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
ICC
additional
supply current
per input pin;
VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
-
60
216
-
270
-
294
A
CI
input
capacitance
-
3.5
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Max
(85 C)
Max
(125 C)
-
25
90
115
135
74HC08
tpd
propagation delay nA, nB to nY; see Figure 6
[1]
VCC = 2.0 V
VCC = 4.5 V
-
9
18
23
27
ns
VCC = 5.0 V; CL = 15 pF
-
7
-
-
-
ns
-
7
15
20
23
ns
VCC = 6.0 V
tt
transition time
74HC_HCT08
Product data sheet
ns
see Figure 6
[2]
VCC = 2.0 V
-
19
75
95
110
ns
VCC = 4.5 V
-
7
15
19
22
ns
VCC = 6.0 V
-
6
13
16
19
ns
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 15
74HC08; 74HCT08
NXP Semiconductors
Quad 2-input AND gate
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
CPD
25 C
Conditions
power dissipation
capacitance
40 C to +125 C Unit
Min
Typ
Max
Max
(85 C)
Max
(125 C)
-
10
-
-
-
VCC = 4.5 V
-
14
24
30
36
ns
VCC = 5.0 V; CL = 15 pF
-
11
-
-
-
ns
[3]
per package; VI = GND to VCC
pF
74HCT02
[1]
propagation delay nA, nB to nY; see Figure 6
tpd
transition time
tt
power dissipation
capacitance
CPD
VCC = 4.5 V; see Figure 6
[2]
-
7
15
19
22
ns
per package;
VI = GND to VCC 1.5 V
[3]
-
20
-
-
-
pF
[1]
tpd is the same as tPHL and tPLH.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9,
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90
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92+
W3/+
9<
90
9;
Q
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