74HC123D

74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Rev. 05 — 13 July 2009 Product data sheet 1. General description The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output pulse width control by three methods: 1. The basic pulse is programmed by selection of an external resistor (REXT) and capacitor (CEXT). 2. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. Alternatively an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering. 3. An internal connection from nRD to the input gates makes it possible to trigger the circuit by a HIGH-going signal at input nRD as shown in the function table. Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower input rise and fall times. The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered via the reset input. 2. Features I I I I I DC triggered from active HIGH or active LOW inputs Retriggerable for very long pulses up to 100 % duty factor Direct reset terminates output pulse Schmitt-trigger action on all inputs except for the reset input ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and from −40 °C to +125 °C NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 3. Ordering information Table 1. Ordering information Package Temperature range Name 74HC123N 74HCT123N 74HC123D 74HCT123D 74HC123DB 74HCT123DB 74HC123PW 74HCT123PW 74HC123BQ −40 °C to +125 °C DHVQFN16 −40 °C to +125 °C TSSOP16 −40 °C to +125 °C SSOP16 −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT109-1 SOT338-1 SOT403-1 SOT763-1 −40 °C to +125 °C DIP16 Description plastic dual in-line package; 16 leads (300 mil) Version SOT38-4 Type number 4. Functional diagram 14 15 S 1A 1 T 2 Q 4 Q 1CEXT 1REXT/CEXT 13 1Q 1Q 1B RD 3 6 7 S 2CEXT 1RD 2REXT/CEXT 2A 9 T 10 Q 5 2Q Q 12 2Q 2B RD 11 001aaa610 2RD Fig 1. Functional diagram 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 2 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 14 15 1 2 1CEXT 14 2CEXT 6 3 CX RCX & 4 R 13 1REXT/CEXT 15 2REXT/CEXT S 1 1A 9 2A 2 1B 10 2B 3 1RD 11 2RD T Q 1Q 4 2Q 12 11 mna515 7 6 CX RCX & 12 R mna516 Q 1Q 13 2Q 5 7 9 10 5 RD Fig 2. Logic symbol Fig 3. IEC logic symbol nREXT/CEXT VCC nRD R CL R CL nQ nQ VCC VCC R CL nA CL CL nB R mna518 Fig 4. 74HC_HCT123_5 Logic diagram © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 3 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 5. Pinning information 5.1 Pinning 74HC123 terminal 1 index area 1B 16 VCC 15 1REXT/CEXT 14 1CEXT 13 1Q 12 2Q 11 2RD 10 2B 9 001aaa698 74HC123 74HCT123 1A 1B 1RD 1Q 2Q 2CEXT 2REXT/CEXT GND 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 GND 2A 9 VCC(1) 16 VCC 15 1REXT/CEXT 14 1CEXT 13 1Q 12 2Q 11 2RD 10 2B 1RD 1Q 2Q 2CEXT 2REXT/CEXT 1 1A 2A 001aaf046 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 5. Pin configuration for DIP16, SO16, SSOP16 and TSSOP16 Fig 6. Pin configuration for DHVQFN16 5.2 Pin description Table 2. Symbol 1A 1B 1RD 1Q 2Q 2CEXT 2REXT/CEXT GND 2A 2B 2RD 2Q 1Q 1CEXT 1REXT/CEXT VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description negative-edge triggered input 1 positive-edge triggered input 1 direct reset LOW and positive-edge triggered input 1 active LOW output 1 active HIGH output 2 external capacitor connection 2 external resistor and capacitor connection 2 ground (0 V) negative-edge triggered input 2 positive-edge triggered input 2 direct reset LOW and positive-edge triggered input 2 active LOW output 2 active HIGH output 1 external capacitor connection 1 external resistor and capacitor connection 1 supply voltage 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 4 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 6. Functional description Table 3. Input nRD L X X H H ↑ [1] Function table[1] Output nA X H X L ↓ L nB X X L ↑ H H nQ L L[2] L[2] nQ H H[2] H[2] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition; = one HIGH level output pulse; = one LOW level output pulse. [2] If the monostable was triggered before this condition was established, the pulse will continue as programmed. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP16 package SO16 package SSOP16 package TSSOP16 package DHVQFN16 package [1] [2] [3] [4] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 °C. [1] [2] [3] [3] [4] Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V except for pins nREXT/CEXT; VO = −0.5 V to (VCC + 0.5 V) Min −0.5 −65 - Max +7 ±20 ±20 ±25 50 −50 +150 750 500 500 500 500 Unit V mA mA mA mA mA °C mW mW mW mW mW 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 5 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 8. Recommended operating conditions Table 5. Recommended operating conditions Conditions Min VCC VI VO ∆t/∆V supply voltage input voltage output voltage input transition rise and fall rate nRD input VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Tamb ambient temperature −40 1.67 +25 625 139 83 +125 −40 1.67 +25 139 +125 ns/V ns/V ns/V °C 2.0 0 0 74HC123 Typ 5.0 Max 6.0 VCC VCC Min 4.5 0 0 74HCT123 Typ 5.0 Max 5.5 VCC VCC V V V Unit Symbol Parameter 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC123 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level VI = VIH or VIL output voltage IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −4 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level VI = VIH or VIL output voltage IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC input leakage current VI = VCC or GND; VCC = 6.0 V 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 1.2 2.4 3.2 0.8 2.1 2.8 2.0 4.5 6.0 4.32 5.81 0 0 0 0.15 0.16 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1.0 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1.0 160 V V V V V V V V V V V V V V V V µA µA Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 6 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V Conditions Min 25 °C Typ 3.5 Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max pF 74HCT123 VIH VIL VOH 2.0 1.6 1.2 0.8 2.0 0.8 2.0 0.8 V V HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −20 µA IO = −4 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 µA IO = 4.0 mA input leakage current VI = VCC or GND; VCC = 5.5 V 4.4 3.98 - 4.5 4.32 0 0.15 - 0.1 0.26 ±0.1 8.0 4.4 3.84 - 0.1 0.33 ±1.0 80 4.4 3.7 - 0.1 0.4 ±1.0 160 V V V V µA µA VOL II ICC ∆ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; IO = 0 A; supply current VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V pins nA, nB pin nRD - 35 50 3.5 125 180 - - 160 225 - - 170 245 - µA µA pF CI input capacitance 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 7 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter 74HC123 tpd propagation delay nRD, nA, nB to nQ or nQ; CEXT = 0 pF; REXT = 5 kΩ; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 5 V; CL = 15 pF VCC = 6.0 V nRD (reset) to nQ or nQ; CEXT = 0 pF; REXT = 5 kΩ; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 5 V; CL = 15 pF VCC = 6.0 V tt output see Figure 9 transition time VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width nA LOW; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nB HIGH; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nRD LOW; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nQ HIGH and nQ LOW; VCC = 5.0 V; see Figure 10 and 11 CEXT = 100 nF; REXT = 10 kΩ CEXT = 0 pF; REXT = 5 kΩ 74HC_HCT123_5 Conditions Min [1] 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 83 30 26 24 255 51 43 - 320 64 54 - 385 77 65 ns ns ns ns [1] 66 24 20 19 19 7 6 8 3 2 17 6 5 14 5 4 215 43 37 75 15 13 - 125 25 21 125 25 21 125 25 21 270 54 46 95 19 16 - 150 30 26 150 30 26 150 30 26 325 65 55 110 22 19 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 20 17 100 20 17 100 20 17 [2] - 450 75 - - - - - µs ns © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 8 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter trtrig retrigger time Conditions Min nA, nB; CEXT = 0 pF; REXT = 5 kΩ; VCC = 5.0 V; see Figure 10 [3][4] 25 °C Typ 110 Max - −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max ns REXT external timing see Figure 7 resistor VCC = 2.0 V VCC = 5.0 V external timing VCC = 5.0 V; see Figure 7 capacitor power dissipation capacitance HIGH to LOW propagation delay per monostable; VI = GND to VCC [4] 10 2 - 54 1000 1000 - - - - - kΩ kΩ pF pF CEXT CPD [5] 74HCT123 tPHL nRD, nA, nB to nQ or nQ; CEXT = 0 pF; REXT = 5 kΩ; see Figure 9 VCC = 4.5 V VCC = 5 V; CL = 15 pF nRD (reset) to nQ or nQ; CEXT = 0 pF; REXT = 5 kΩ; see Figure 9 VCC = 4.5 V VCC = 5 V; CL = 15 pF tPLH LOW to HIGH propagation delay nRD, nA, nB to nQ or nQ; CEXT = 0 pF; REXT = 5 kΩ; see Figure 9 VCC = 4.5 V VCC = 5 V; CL = 15 pF nRD (reset) to nQ or nQ; CEXT = 0 pF; REXT = 5 kΩ; see Figure 9 VCC = 4.5 V VCC = 5 V; CL = 15 pF tt output VCC = 4.5 V; see Figure 9 transition time [1] - 30 26 51 - - 64 - - 77 - ns ns - 27 23 46 - - 58 - - 69 - ns ns - 28 26 51 - - 64 - - 77 - ns ns - 23 23 7 46 15 - 58 19 - 69 22 ns ns ns 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 9 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter tW pulse width Conditions Min VCC = 4.5 V nA LOW; see Figure 10 nB HIGH; see Figure 10 nRD LOW; see Figure 11 nQ HIGH and nQ LOW; VCC = 5.0 V; see Figure 10 and 11 CEXT = 100 nF; REXT = 10 kΩ CEXT = 0 pF; REXT = 5 kΩ trtrig retrigger time nA, nB; CEXT = 0 pF; REXT = 5 kΩ; VCC = 5.0 V; see Figure 10 [3][4] [2] 25 °C Typ 3 5 7 Max - −40 °C to +85 °C −40 °C to +125 °C Unit Min 25 25 25 Max Min 30 30 30 Max ns ns ns 20 20 20 - 450 75 110 - - - - - µs ns ns REXT CEXT CPD external timing VCC = 5.0 V; see Figure 7 resistor external timing VCC = 5.0 V; see Figure 7 capacitor power dissipation capacitance per monostable; VI = GND to VCC [4] 2 - 56 1000 - - - - - kΩ pF pF [5] [1] [2] tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH For other REXT and CEXT combinations see Figure 7. If CEXT > 10 nF, the next formula is valid. tW = K × REXT × CEXT, where: tW = typical output pulse width in ns; REXT = external resistor in kΩ; CEXT = external capacitor in pF; K = constant = 0.45 for VCC = 5.0 V and 0.55 for VCC = 2.0 V. The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF. The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF, the next formula (at VCC = 5.0 V) for the setup time of a retrigger pulse is valid: trtrig = 30 + 0.19 × REXT × CEXT0.9 + 13 × REXT1.05, where: trtrig = retrigger time in ns; CEXT = external capacitor in pF; REXT = external resistor in kΩ. The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF. When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) + 0.75 × CEXT × VCC2 × fo + D × 16 × VCC where: fi = input frequency in MHz; fo = output frequency in MHz; D = duty factor in %; CL = output load capacitance in pF; VCC = supply voltage in V; CEXT = timing capacitance in pF; ∑(CL × VCC2 × fo) sum of outputs. © NXP B.V. 2009. All rights reserved. [3] [4] [5] 74HC_HCT123_5 Product data sheet Rev. 05 — 13 July 2009 10 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 106 tW (ns) 105 001aaa611 0.8 'K' factor 001aaa612 (1) (2) (3) 0.6 104 (4) 0.4 103 0.2 102 10 1 10 102 104 103 CEXT (pF) 0 0 2 4 6 VCC (V) 8 VCC = 5.0 V; Tamb = 25 °C. (1) REXT = 100 kΩ (2) REXT = 50 kΩ (3) REXT = 10 kΩ (4) REXT = 2 kΩ CEXT = 10 nF; REXT = 10 kΩ to 100 kΩ. Tamb = 25 °C. Fig 7. Typical output pulse width as a function of the external capacitor value Fig 8. 74HC123 typical ‘K’ factor as function of VCC 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 11 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 11. Waveforms VI nB input GND tW VI nA input GND tW VI nRD input GND tPLH VOH nQ output VOL tTHL tW VOH nQ output VOL tPHL tPHL VM VX tTLH tPLH (reset) tPHL 001aaa771 VM VM VM tPLH tW VY VM VX tPHL (reset) tW VY tPLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) and output transition times 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 12 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset nB input tW nA input trtrig tW nQ output tW tW tW mna521 nRD = HIGH Fig 10. Output pulse control using retrigger pulse nB input nRD input tW nQ output tW tW mna522 nA = LOW Fig 11. Output pulse control using reset input nRD 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 13 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 8. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 12. Test circuit for measuring switching times Table 8. Type 74HC123 74HCT123 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 14 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 12. Application information 12.1 Timing component connections The basic output pulse width is essentially determined by the values of the external timing components REXT and CEXT. CEXT (1) REXT VCC nCEXT 14 (6) nREXT/CEXT 15 (7) 13 (5) nQ GND 8 123 nA nB 1 (9) 2 (10) 4 (12) nQ 3 (11) nRD 001aaa854 (1) For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND). Fig 13. Timing component connections 12.2 Power-up considerations When the monostable is powered-up it may produce an output pulse, with a pulse width defined by the values of REXT and CEXT. This output pulse can be eliminated using the circuit shown in Figure 14. CEXT REXT VCC GND 8 nCEXT 14 (6) nREXT/CEXT 15 (7) 13 (5) nQ 123 nA nB 1 (9) 2 (10) 4 (12) nQ 3 (11) nRD RESET VCC 001aaa613 Fig 14. Power-up output pulse elimination circuit 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 15 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 12.3 Power-down considerations A large capacitor CEXT may cause problems when powering-down the monostable due to the energy stored in this capacitor. When a system containing this device is powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain damage, due to the capacitor discharging through the input protection diodes. To avoid this possibility, use a damping diode (DEXT) preferably a germanium or Schottky type diode able to withstand large current surges and connect as shown in Figure 15. DEXT CEXT REXT VCC GND 8 nCEXT 14 (6) nREXT/CEXT 15 (7) 13 (5) nQ 123 nA nB 1 (9) 2 (10) 4 (12) nQ 3 (11) 001aaa614 nRD Fig 15. Power-down protection circuit 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 16 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 16. Package outline SOT38-4 (DIP16) 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 17 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 17. Package outline SOT109-1 (SO16) 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 18 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 18. Package outline SOT338-1 (SSOP16) 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 19 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 19. Package outline SOT403-1 (TSSOP16) 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 20 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 20. Package outline SOT763-1 (DHVQFN16) 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 21 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 14. Abbreviations Table 9. Acronym CMOS DUT ESD HBM LSTTL MM Abbreviations Abbreviation Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model 15. Revision history Table 10. Revision history Release date 20090713 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT123_4 Document ID 74HC_HCT123_5 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3 “Ordering information” and Section 13 “Package outline”, package version SOT38-1 changed to SOT38-4 Product data sheet Product specification Product specification 74HC_HCT123_3 74HC_HCT123_CNV_2 - 74HC_HCT123_4 74HC_HCT123_3 74HC_HCT123_CNV_2 20060616 20040511 19980708 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 22 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT123_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 13 July 2009 23 of 24 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 12.1 12.2 12.3 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information. . . . . . . . . . . . . . . . . . 15 Timing component connections . . . . . . . . . . . 15 Power-up considerations . . . . . . . . . . . . . . . . 15 Power-down considerations . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 July 2009 Document identifier: 74HC_HCT123_5