74HC157D-Q100,118

74HC157-Q100; 74HCT157-Q100 Quad 2-input multiplexer Rev. 2 — 21 January 2015 Product data sheet 1. General description The 74HC157-Q100; 74HCT157-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT157-Q100 are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74HC/HCT157-Q100. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The 74HC/HCT157-Q100 is logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The logic equations are: 1Y = E (1I1 S + 1I0 S) 2Y = E (2I1 S + 2I0 S) 3Y = E (3I1 S + 3I0 S) 4Y = E (4I1 S + 4I0 S) This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Low-power dissipation  Non-inverting data path  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options 74HC157-Q100; 74HCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 3. Ordering information Table 1. Ordering information Type number 74HC157D-Q100 Package Temperature range Name Description 40 C to +125 C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm 74HCT157D-Q100 74HC157PW-Q100 74HCT157PW-Q100 74HC157BQ-Q100 74HCT157BQ-Q100 Version 4. Functional diagram 6 ( , < , , < ,  ,        < , , , , , , , , ,   6  ( , < < < <     < , Fig 1. PQD Logic diagram 74HC_HCT157_Q100 Product data sheet PQD Fig 2. logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 17 74HC157-Q100; 74HCT157-Q100 NXP Semiconductors Quad 2-input multiplexer   ,  ,  ,  ,  ,  ,  ,  , 6(/(&725 <   <   * (1   08/7,3/(;(5 2873876 < 08;        <     Fig 3. 6 (     PQD Logic symbol PQD Fig 4. IEC logic symbol 5. Pinning information 5.1 Pinning  6 WHUPLQDO LQGH[DUHD +&4 +&74  9&& +&4 +&74 ,   ( 6    ,   9&&  ( , , <   , ,   , ,   < <   , ,  ,   < ,   , <  <   , *1'    < <  ,  , *1'  *1' DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO16, TSSOP16 74HC_HCT157_Q100 Product data sheet Fig 6. Pin configuration DHVQFN16 All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 17 74HC157-Q100; 74HCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 5.2 Pin description Table 2. Pin description Symbol Pin Description S 1 common data select input 1I0 to 4I0 2, 5, 11, 14 data inputs from source 0 1I1 to 4I1 3, 6, 10, 13 data inputs from source 1 1Y to 4Y 4, 7, 9, 12 multiplexer outputs GND 8 ground (0 V) E 15 enable input (active LOW) VCC 16 supply voltage 6. Functional description Table 3. Function table[1] Input Output E S nI0 nI1 nY H X X X L L L L X L L L H X H L H X L L L H X H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC supply voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V IO output current VO = 0.5 V to (VCC + 0.5 V) ICC supply current - +50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C Ptot total power dissipation [1] Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA Tamb = 40 C to +125 C SO16 package [1] - 500 mW TSSOP16 package [2] - 500 mW DHVQFN16 package [3] - 500 mW Ptot derates linearly with 8 mW/K above 70 C. [2] Ptot derates linearly with 5.5 mW/K above 60 C. [3] Ptot derates linearly with 4.5 mW/K above 60 C. 74HC_HCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 17 NXP Semiconductors 74HC157-Q100; 74HCT157-Q100 Quad 2-input multiplexer 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC157-Q100 Min Typ 74HCT157-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Min Typ Tamb = 40 C to +85 C Tamb = 40 C to Unit +125 C Max Min Max Min Max - 1.5 - 74HC157-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 1.2 - 1.5 V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V VI = VIH or VIL IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A 74HC_HCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 17 74HC157-Q100; 74HCT157-Q100 NXP Semiconductors Quad 2-input multiplexer Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Min Typ CI input capacitance Tamb = 40 C to +85 C Max - 3.5 - Min Max Tamb = 40 C to Unit +125 C Min Max pF 74HCT157-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; nI0, nI1 inputs - 100 360 - 450 - 490 A per input pin; E input - 60 216 - 270 - 294 A per input pin; S input - 100 360 - 450 - 490 A - 3.5 - VOL CI input capacitance 74HC_HCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 January 2015 pF © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 17 74HC157-Q100; 74HCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max - 36 125 - 155 - 190 ns VCC = 4.5 V - 13 25 - 31 - 38 ns VCC = 5 V; CL = 15 pF - 11 - - - - - ns - 10 21 - 26 - 32 ns VCC = 2.0 V - 41 125 - 155 - 190 ns VCC = 4.5 V - 15 25 - 31 - 38 ns VCC = 5 V; CL = 15 pF - 12 - - - - - ns - 12 21 - 26 - 32 ns VCC = 2.0 V - 39 115 - 145 - 175 ns VCC = 4.5 V - 14 23 - 29 - 35 ns VCC = 5 V; CL = 15 pF - 11 - - - - - ns - 11 20 - 25 - 30 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns 74HC157-Q100 tpd propagation delay nI0, nI1 to nY; see Figure 7 [1] VCC = 2.0 V VCC = 6.0 V [1] S to nY; see Figure 7 VCC = 6.0 V [1] E to nY; see Figure 8 VCC = 6.0 V tt transition time [2] nY; see Figure 7 VCC = 6.0 V CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC [3] nI0, nI1 to nY; see Figure 7 [1] - 6 13 - 16 - 19 ns - 70 - - - - - pF - 16 27 - 34 - 41 ns - 13 - - - - - ns - 22 37 - 46 - 56 ns - 19 - - - - - ns 74HCT157-Q100 tpd propagation delay VCC = 4.5 V VCC = 5 V; CL = 15 pF S to nY; see Figure 7 [1] VCC = 4.5 V VCC = 5 V; CL = 15 pF E to nY; see Figure 8 74HC_HCT157_Q100 Product data sheet [1] VCC = 4.5 V - 15 26 - 33 - 39 ns VCC = 5 V; CL = 15 pF - 12 - - - - - ns All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 17 74HC157-Q100; 74HCT157-Q100 NXP Semiconductors Quad 2-input multiplexer Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9. Symbol Parameter tt transition time power dissipation capacitance CPD [1] Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max - 7 15 - 19 - 22 ns - 70 - - - - - pF [2] nY; see Figure 7 VCC = 4.5 V [3] CL = 50 pF; f = 1 MHz; VI = GND to VCC  1.5 V tpd is the same as tPLH and tPHL. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 11. Waveforms 9, LQSXW 6Q,Q, 90 90 *1' W 3+/ W 3/+ 92+ RXWSXW Q<  90 90  92/ W 7+/ W 7/+ DDG Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay input (nI0, nI1, S) to output (nYn) 74HC_HCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 17 74HC157-Q100; 74HCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 9&& 90 (LQSXW *1' W 3+/ W 3/+ 92+ 90 Q