74HC163N,652

74HC163; 74HCT163 Presettable synchronous 4-bit binary counter; synchronous reset Rev. 3 — 2 June 2014 Product data sheet 1. General description The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula: 1 f max = ---------------------------------------------------------------------------------------t P  max   CPtoTC  + t SU  CEPtoCP  2. Features and benefits  Complies with JEDEC standard no. 7A  Input levels:  For 74HC163: CMOS level  For 74HCT163: TTL level  Synchronous counting and loading  2 count enable inputs for n-bit cascading  Synchronous reset  Positive-edge triggered clock  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 3. Ordering information Table 1. Ordering information Type number 74HC163N Package Temperature range Name Description Version 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT163N 74HC163D 74HCT163D 74HC163DB 74HCT163DB 74HC163PW 74HCT163PW 4. Functional diagram  '  '  '  '      ' ' '  3( 3$5$//(/ /2$'&,5&8,75<  05  3( ' &(3  &(7   &(3  &3  05 ' ,1+  &3 &3 4  Fig 1. 7&  %,1$5< &2817(5 4  4  &(7 7&  4 4 4 4 4   DDD Functional diagram      5   DDD Fig 2.   Logic symbol &75 0 * * &  '       &7   DDD Fig 3. IEC logic symbol 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 24 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x ' ' NXP Semiconductors 74HC_HCT163 Product data sheet ' ' &(7 &(3 05 ' ' &3 ))  4 ' &3 4 ' &3 4 3 of 24 © NXP Semiconductors N.V. 2014. All rights reserved. 4 ))  4 &3 4 4 ))  4 4 4 4 7& DDD Fig 4. Logic diagram 74HC163; 74HCT163 &3 ))  4 Presettable synchronous 4-bit binary counter; synchronous reset Rev. 3 — 2 June 2014 All information provided in this document is subject to legal disclaimers. 3( 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 5. Pinning information 5.1 Pinning +& +&7 +& +&7 05   9&& 05   9&& &3   7& &3   7& '   ' '   ' '   4 '   4 '  4  '   4 &(3   &(7 *1'   3( '   4 '   4 &(3   &(7 *1'   DDD Fig 5. Pin configuration DIP16 3( +& +&7 05   9&& &3   7& '   ' '   4 '   4 '   4 &(3   &(7 *1'  Fig 6. Pin configuration SO16  3( DDD DDD Fig 7. Pin configuration TSSOP16 and SSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 synchronous master reset (active LOW) CP 2 clock input (LOW-to-HIGH, edge triggered) D0, D1, D2, D3 3, 4, 5, 6 data input CEP 7 count enable input GND 8 ground (0 V) PE 9 parallel enable input (active LOW) CET 10 count enable carry input Q0, Q1, Q2, Q3 14, 13, 12, 11 flip-flop output TC 15 terminal count output VCC 16 supply voltage 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 6. Functional description Table 3. Function table[1] Operating mode Inputs Outputs MR CP CEP CET PE Dn Qn TC Reset (clear) I  X X X X L L Parallel load h  X X I I L L h  X X I h H L Count h  h h h X count Hold (do nothing) h X I X h X qn L h X X I h X qn L [1] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH); H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition; X = don’t care;  = LOW-to-HIGH clock transition.                 DDD Fig 8. State diagram 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 05 3( ' ' ' ' &3 &(3 &(7 4 4 4 4 7&   UHVHW SUHVHW    FRXQW   LQKLELW DDD Sequence reset outputs to zero; preset to binary 12; count to 13, 14, 15, zero, one and two; inhibit. Fig 9. Typical timing sequence 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7.0 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature total power dissipation Ptot [1] 65 +150 C DIP16 package [1] - 750 mW SO16 package [1] - 500 mW (T)SSOP16 package [1] - 500 mW For DIP16 packages: above 70 C the value of Ptot derates linearly at 12 mW/K. For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K. For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K. 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC163 Min 74HCT163 Typ Max Min Unit Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 3.15 VCC = 6.0 V 4.2 VCC = 2.0 V - VCC = 4.5 V - VCC = 6.0 V 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 2.4 - 3.15 - 3.15 - V 3.2 - 4.2 - 4.2 - V 0.8 0.5 - 0.5 - 0.5 V 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A - - 8.0 - 80.0 - 160.0 A 74HC163 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min CI input capacitance Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max - 3.5 - - - - - pF 74HCT163 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V 3.98 4.32 - 3.84 - 3.7 - V - 0 0.1 - 0.1 - 0.1 V - 0.15 0.26 - 0.33 - 0.4 V - - 0.1 - 1.0 - 1.0 A - - 8.0 - 80.0 - 160.0 A pin MR - 95 342 - 427.5 - 465.5 A IO = 4.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A IO = 4.0 mA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V ICC additional per input pin; VI = VCC  2.1 V; supply current other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A CI input capacitance 74HC_HCT163 Product data sheet VI = VCC or GND; VCC = 5.5 V pin CP - 110 396 - 495 - 539 A pin CEP and Dn - 25 90 - 112.5 - 122.5 A pin CET - 75 270 - 337.5 - 367.5 A pin PE - 30 108 - 135 - 147 A - 3.5 - - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 15. Symbol Parameter 25 C Conditions Min 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max - 55 185 - 230 - 280 ns - 20 37 - 46 - 56 ns 74HC163 tpd [1] propagation CP to Qn; see Figure 10 delay VCC = 2.0 V VCC = 4.5 V - VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 31 - 39 - 48 ns VCC = 2.0 V - 69 215 - 270 - 320 ns VCC = 4.5 V - 25 43 - 54 - 65 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns VCC = 6.0 V - 20 37 - 46 - 55 ns CP to TC; see Figure 10 CET to TC; see Figure 11 VCC = 2.0 V - 36 120 - 150 - 180 ns VCC = 4.5 V - 13 24 - 30 - 36 ns VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns - 10 20 - 26 - 31 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 6.0 V tt tW transition time pulse width 74HC_HCT163 Product data sheet see Figure 10 and Figure 11 [2] CP; HIGH or LOW; see Figure 10 All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 15. Symbol Parameter tsu set-up time 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 175 58 - 220 - 265 - ns VCC = 4.5 V 35 21 - 44 - 53 - ns VCC = 6.0 V 30 17 - 37 - 45 - ns MR, Dn to CP; see Figure 12 and Figure 13 PE to CP; see Figure 12 CEP, CET to CP; see Figure 14 th fmax hold time maximum frequency Dn, PE, CEP, CET, MR to CP; see Figure 12, Figure 13 and Figure 14 VCC = 2.0 V 0 14 - 0 - 0 - ns VCC = 4.5 V 0 5 - 0 - 0 - ns VCC = 6.0 V 0 4 - 0 0 - ns VCC = 2.0 V 5 15 - 4 - 4 - MHz VCC = 4.5 V 27 46 - 22 - 18 - MHz - 51 - - - - - MHz 32 55 - 26 - 21 - MHz - 33 - - - - - pF CP; see Figure 10 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD power VI = GND to VCC; VCC = 5 V; dissipation fi = 1 MHz capacitance 74HC_HCT163 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 15. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 23 39 - 49 - 59 ns - 20 - - - - - ns VCC = 4.5 V - 29 49 - 61 - 74 ns VCC = 5.0 V; CL = 15 pF - 25 - - - - - ns - 17 32 - 44 - 48 ns - 14 - - - - - ns - 7 15 - 19 - 22 ns 20 6 - 25 - 30 - ns 20 9 - 25 - 30 - ns 20 11 - 25 - 30 - ns 40 24 - 50 - 60 - ns 0 5 - 0 - 0 - ns 26 45 - 21 - 17 - MHz - 50 - - - - - MHz 74HCT193 tpd [1] propagation CP to Qn; see Figure 10 delay VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CP to TC; see Figure 10 CET to TC; see Figure 11 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt tW transition time see Figure 10 and Figure 11 pulse width CP; HIGH or LOW; see Figure 10 VCC = 4.5 V VCC = 4.5 V tsu set-up time [2] MR, Dn to CP; see Figure 12 and Figure 13 VCC = 4.5 V PE to CP; see Figure 12 VCC = 4.5 V CEP, CET to CP; see Figure 14 VCC = 4.5 V th hold time Dn, PE, CEP, CET, MR to CP; see Figure 12, Figure 13 and Figure 14 VCC = 4.5 V fmax maximum frequency CP; see Figure 10 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 15. Symbol Parameter power VI = GND to VCC  1.5 V; dissipation VCC = 5 V; fi = 1 MHz capacitance CPD [1] 25 C Conditions [3] 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 35 - - - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 11. Waveforms IPD[ 9, &3LQSXW 90 *1' W: W3+/ 92+ 4Q7& RXWSXW W3/+   90 92/   W7+/ W7/+ DDD Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum frequency 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 9, &(7LQSXW 90 *1' W3/+ W3+/ 92+  7&RXWSXW  90  92/  W7/+ W7+/ DDD Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. The count enable carry input (CET) to terminal count output (TC) propagation delays and output transition times 9, 90 3(LQSXW *1' WVX WVX WK WK 9, 90 &3LQSXW *1' WVX WVX WK 9, WK 90 'QLQSXW *1' DDD The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Fig 12. The data input (Dn) and parallel enable input (PE) set-up and hold times 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 9, 90 05LQSXW *1' WVX WVX WK 9, &3LQSXW WK 90 *1' DDD The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Fig 13. The master reset (MR) set-up and hold times 9, &(3&(7 LQSXW 90 *1' 9, &3LQSXW WVX WVX WK WK 90 *1' DDD The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Fig 14. The count enable input (CEP) and count enable carry input (CET) set-up and hold times Table 8. Measurement points Type Input Output VM VI VM 74HC163 0.5  VCC GND to VCC 0.5  VCC 74HCT163 1.3 V GND to 3 V 1.3 V 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 9, W:  QHJDWLYH SXOVH 90 9 9, WI WU WU WI  SRVLWLYH SXOVH 9 90  90 90  W: 9&& 9&& * 9, 92 5/ 6 RSHQ '87 &/ 57 DDG Test data is given in Table 9. Test circuit definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistance. S1 = Test selection switch Fig 15. Test circuit for measuring switching times Table 9. Test data Type Input VI tr, tf CL RL tPHL, tPLH 74HC163 VCC 6 ns 15 pF, 50 pF 1 k open 74HCT163 3V 6 ns 15 pF, 50 pF 1 k open 74HC_HCT163 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 S1 position © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 12. Application information The 74HC163; 74HCT63 facilitate designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous reset. RWKHU LQSXWV 4 4 RXWSXW 4 4 UHVHW DDD Fig 16. Modulo-5 counter RWKHU LQSXWV 4 4 4 RXWSXW 4 UHVHW DDD Fig 17. Modulo-11 counter 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 13. Package outline ',3SODVWLFGXDOLQOLQHSDFNDJHOHDGVPLO 627 0( VHDWLQJSODQH ' $ $ $ / F H = Z 0 E E  H  E  0+ SLQLQGH[ (     PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $  PLQ $  PD[ E E E F ' ( H H / 0( 0+ Z = PD[ PP                          LQFKHV                          1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627   -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 18. Package outline SOT38-4 (DIP16) 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 17 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S  /  H Z 0 ES   GHWDLO; PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP                                                 LQFKHV         ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 19. Package outline SOT109-1 (SO16) 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 18 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   GHWDLO; Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 20. Package outline SOT338-1 (SSOP16) 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 19 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 21. Package outline SOT403-1 (TSSOP16) 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 20 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT163 v.3 20140602 Product data sheet - 74HC_HCT163_CNV v.2 Modifications: 74HC_HCT163_CNV v.2 74HC_HCT163 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 19930927 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 - © NXP Semiconductors N.V. 2014. All rights reserved. 21 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT163 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 22 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT163 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 23 of 24 74HC163; 74HCT163 NXP Semiconductors Presettable synchronous 4-bit binary counter; synchronous reset 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information. . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 June 2014 Document identifier: 74HC_HCT163