74HC237D

74HC237 3-to-8 line decoder, demultiplexer with address latches Rev. 4 — 10 January 2011 Product data sheet 1. General description The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC standard no. 7A. The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems. 2. Features and benefits      Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active HIGH mutually exclusive outputs Low-power dissipation ESD protection:  HBM JESD22-A114F exceeds 2 000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Temperature range 74HC237N 74HC237D 74HC237DB 40 C to +125 C 40 C to +125 C 40 C to +125 C Name DIP16 SO16 SSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm Version SOT38-4 SOT109-1 SOT338-1 Type number Package NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches 4. Functional diagram 4 LE Y0 15 Y1 14 1 A0 2 A1 3 A2 INPUT LATCHES 3 TO 8 DECODER Y2 13 Y3 12 Y4 11 Y5 10 Y6 9 Y7 7 5 E1 6 E2 001aab871 Fig 1. Functional diagram DX 4 1 2 4 LE Y0 Y1 1 2 3 A0 A1 A2 INPUT LATCHES Y2 Y3 3 TO 8 DECODER Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 C8 0 0 8D,G 7 2 0 1 2 3 4 5 15 14 13 12 11 10 9 7 3 5 6 & 6 7 X/Y 4 1 2 C8 8D,1 8D,2 8D,4 0 1 2 3 4 5 5 6 EN 001aab870 15 14 13 12 11 10 9 7 E1 5 6 E2 001aab869 3 & 6 7 Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 2 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches A0 A0 LE LATCH A0 LE Y0 Y1 A1 A1 LE LATCH A1 LE Y2 A2 A2 LE LATCH A2 LE Y3 Y4 LE Y5 Y6 Y7 E1 001aab872 E2 Fig 4. Logic diagram 5. Pinning information 5.1 Pinning 74HC237 A0 A1 A2 LE E1 E2 Y7 GND 1 2 3 4 5 6 7 8 001aab868 16 VCC 74HC237 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 A0 A1 A2 LE E1 E2 Y7 GND 1 2 3 4 5 6 7 8 001aan382 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 Fig 5. Pin configuration DIP16 and SO16 Fig 6. Pin configuration SSOP16 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 3 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches 5.2 Pin description Table 2. Symbol A0 to A2 LE E1 E2 Y0 to Y7 GND VCC Pin description Pin 1, 2, 3 4 5 6 8 16 Description data input latch enable input (active LOW) data enable input 1 (active LOW) data enable input 2 (active HIGH) ground (0 V) supply voltage 15, 14, 13, 12, 11, 10, 9, 7 output 6. Functional description Table 3: Enable LE H X X L E1 L H X L E2 H X L H Function table Input A0 X X X L H L H L H L H [1] Output A1 X X X L L H H L L H H A2 X X X L L L L H H H H Y0 stable L L H L L L L L L L L L L H L L L L L L L L L L H L L L L L L L L L L H L L L L L L L L L L H L L L L L L L L L L H L L L L L L L L L L H L L L L L L L L L L H Y1 Y2 Y3 Y4 Y5 Y6 Y7 H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP16 package SO16 and SSOP16 packages 74HC237 All information provided in this document is subject to legal disclaimers. Conditions VI < 0.5 V or VI > VCC + 0.5 V VO < 0.5 V or VO > VCC + 0.5 V VO = 0.5 V to (VCC + 0.5 V) Min 0.5 65 [1] [2] Max +7 20 20 25 +50 50 +150 750 500 Unit V mA mA mA mA mA C mW mW 4 of 17 - © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches [1] [2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol VCC VI VO Tamb t/V Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions Min 2.0 0 0 40 Typ 5.0 +25 1.67 Max 6.0 VCC VCC +125 625 139 83 Unit V V V C ns/V ns/V ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Tamb = 25 C Min VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V 0 0 0 0.15 0.16 0.1 0.1 0.1 0.26 0.26 0.1 0.1 0.1 0.33 0.33 0.1 0.1 0.1 0.4 0.4 V V V V V 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 1.9 4.4 5.9 3.84 5.34 1.9 4.4 5.9 3.7 5.2 V V V V V 1.5 3.15 4.2 Typ 1.2 2.4 3.2 0.8 2.1 2.8 Max 0.5 1.35 1.8 Tamb = 40 C to +85 C Min 1.5 3.15 4.2 Max 0.5 1.35 1.8 Tamb = 40 C to Unit +125 C Min 1.5 3.15 4.2 Max 0.5 1.35 1.8 V V V V V V 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 5 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Tamb = 25 C Min II ICC CI input leakage current supply current input capacitance VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V Typ 3.5 Max 0.1 8.0 Tamb = 40 C to +85 C Min Max 1.0 80 Tamb = 40 C to Unit +125 C Min Max 1.0 160 A A pF 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10. Symbol Parameter Conditions Tamb = 25 C Min tpd propagation delay An to Yn; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5 V; CL = 15 pF VCC = 6.0 V LE to Yn; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5 V; CL = 15 pF VCC = 6.0 V E1to Yn; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 5 V; CL = 15 pF VCC = 6.0 V E2 to Yn; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5 V; CL = 15 pF VCC = 6.0 V tt transition time Yn; see Figure 7 and Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V [2] [1] [1] [1] [1] Tamb = 40 C to +85 C Min Max 200 40 34 240 48 41 180 36 31 180 36 31 Tamb = 40 C to +125 C Min Max 240 48 41 285 57 48 220 44 38 220 44 38 Unit Typ 52 19 16 15 61 22 19 18 47 17 14 14 47 17 14 14 Max 160 32 27 190 38 32 145 29 25 145 29 25 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns - 19 7 6 75 15 13 - 95 19 16 - 110 22 19 ns ns ns 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 6 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10. Symbol Parameter Conditions Tamb = 25 C Min tW pulse width LE HIGH; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time An to LE; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time An to LE; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC [3] Tamb = 40 C to +85 C Min 65 13 11 65 13 11 40 8 7 Max - Tamb = 40 C to +125 C Min 75 15 13 75 15 13 45 9 8 Max - Unit Typ 11 4 3 6 2 2 3 1 1 60 Max - 50 10 9 50 10 9 30 6 5 - ns ns ns ns ns ns ns ns ns pF [1] [2] [3] tpd is the same as tPLH and tPHL. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 11. Waveforms An, E2, LE input VM tPHL Yn output tPLH VM tTHL tTLH 001aab873 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. 74HC237 Propagation delay input (An) and enable inputs (E2, LE) to output (Yn) and output transition time All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 7 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches E1 input VM tPHL Yn output tPLH VM tTHL tTLH 001aab874 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Propagation enable inputs (E1) to output (Yn) and output transition time An input VM th VM latched th tsu LE input transparant tsu transparant tW latched 001aab875 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. The data input (An) to latch enable input (LE) set-up times, latch enable input (LE) to data input (An) hold times and latch enable input (LE) pulse width Measurement points Input VM 0.5VCC Output VM 0.5VCC Table 8. Type 74HC237 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 8 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches VI negative pulse GND tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VCC G VI VO VM VI positive pulse GND VM DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 10. Test circuit for measuring switching times Table 9. Type 74HC237 Test data Input VI VCC tr, tf 6.0 ns Load CL 15 pF, 50 pF tPLH, tPHL Test 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 9 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches 12. Application information strobe decoder enable X0 X1 X2 LE A2 A1 A0 237 E2 E1 input address Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 01234567 X3 X4 X5 to five other decoders LE A2 A1 A0 237 E2 E1 LE A2 A1 A0 237 E2 E1 LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 01234567 outputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 8 9 10 11 12 13 14 15 outputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 16 17 18 19 20 21 22 23 outputs 001aab876 Fig 11. 6-to-64 line decoder with input address storage 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 10 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 12. Package outline SOT38-4 (DIP16) 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 11 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 A1 pin 1 index θ Lp 1 8 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 8o o 0 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT109-1 (SO16) 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 12 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 pin 1 index θ Lp L 1 8 A1 (A 3) A detail X wM e bp 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8o o 0 ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT338-1 (SSOP16) 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 13 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches 14. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date 20110110 Data sheet status Product data sheet Change notice Supersedes 74HC237 v3 Document ID 74HC237 v.4 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Corrected the application drawing. Product data sheet Product specification Product specification 74HC_HCT237_CNV v.2 74HC_HCT237 v.1 - 74HC237 v3 74HC_HCT237_CNV v.2 74HC_HCT237 v.1 20041112 19970828 19901201 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 14 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 15 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 16 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 January 2011 Document identifier: 74HC237