74HC258D

74HC258 Quad 2-input multiplexer; 3-state; inverting Rev. 04 — 14 April 2008 Product data sheet 1. General description The 74HC258 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC258 is specified in compliance with JEDEC standard no. 7A. The 74HC258 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and is controlled by a common data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in inverted form from the select inputs. The 74HC258 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high-impedance OFF-state when OE is HIGH. The logic equations for the outputs are: 1Y = OE × ( 1I1 × S + 1I0 × S ) 2Y = OE × ( 2 I1 × S + 2 I0 × S ) 3Y = OE × ( 3 I1 × S + 3 I0 × S ) 4Y = OE × ( 4 I1 × S + 4 I0 × S ) The 74HC258 is identical to the 74HC257 but has inverting outputs. 2. Features I I I I I 3-state outputs interface directly with system bus Low-power dissipation Inverting data path Complies with JEDEC standard no. 7A ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C. NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 3. Ordering information Table 1. Ordering information Temperature range 74HC258N 74HC258D 74HC258DB −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name DIP16 SO16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1 SOT338-1 Type number Package SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 4. Functional diagram 1 3 5 6 11 10 14 13 2 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 1S SELECTOR 2 3 5 6 11 S 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 OE 001aab966 1Y 4 2Y 7 15 OE 10 3-STATE MULTIPLEXER OUTPUTS 14 13 3Y 9 4Y 12 1Y 4 2Y 7 3Y 9 4Y 12 001aab968 15 Fig 1. Functional diagram Fig 2. Logic symbol 1I0 1Y 1I1 1 15 G1 EN MUX 2I0 2Y 2 3 5 1 1 2I1 4 3I0 7 6 11 9 10 14 12 13 001aab967 3Y 3I1 4I0 4Y 4I1 OE S 001aab969 Fig 3. 74HC258_4 IEC logic symbol Fig 4. Logic diagram © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 2 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 5. Pinning information 5.1 Pinning S 1I0 1I1 1Y 2I0 2I1 2Y GND 1 2 3 4 16 VCC 15 OE 14 4I0 13 4I1 258 5 6 7 8 001aab904 12 4Y 11 3I0 10 3I1 9 3Y Fig 5. Pin configuration 5.2 Pin description Table 2. Symbol S 1I0 1I1 1Y 2I0 2I1 2Y GND 3Y 3I1 3I0 4Y 4I1 4I0 OE VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description common data select input data input 1 from source 0 data input 1 from source 1 3-state multiplexer output 1; inverted data input 2 from source 0 data input 2 from source 1 3-state multiplexer output 2; inverted ground (0 V) 3-state multiplexer output 3; inverted data input 3 from source 1 data input 3 from source 0 3-state multiplexer output 4; inverted data input 4 from source 1 data input 4 from source 0 output enable input (active LOW) positive supply voltage 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 3 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 6. Functional description Table 3. Control OE H L L L L [1] Function table[1] Input S X L L H H nl0 X L H X X nI1 X X X L H Output nY Z H L H L H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C DIP16 package SO16 package SSOP16 package [1] [2] [3] [4] [2] [3] [4] Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to VCC + 0.5 V [1] [1] Min −0.5 −70 −65 - Max +7.0 ±20 ±20 ±35 70 +150 750 500 500 Unit V mA mA mA mA mA °C mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 12 mW/K above 70 °C. Ptot derates linearly with 8 mW/K above 70 °C. Ptot derates linearly with 5.5 mW/K above 60 °C. 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 4 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 8. Recommended operating conditions Table 5. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions Min 2.0 0 0 −40 Typ 5.0 1.67 Max 6.0 VCC VCC +125 625 139 83 Unit V V V °C ns ns ns 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions Min VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −6 mA; VCC = 4.5 V IO = −7.8 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 6 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V II IOZ ICC CI input leakage current OFF-state output current VI = VCC or GND; VCC = 6.0 V VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND; IO = 0 A 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.33 0.33 ±1.0 ±5.0 80 0.1 0.1 0.1 0.4 0.4 ±1.0 ±10 160 V V V V V µA µA µA pF 1.9 4.4 5.9 2.0 4.5 6.0 1.9 4.4 5.9 3.84 5.34 1.9 4.4 5.9 3.7 5.2 V V V V V 1.5 3.15 4.2 25 °C Typ Max 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 −40 °C to +85 °C Min 1.5 3.15 4.2 Max 0.5 1.35 1.8 −40 °C to +125 °C Unit Min 1.5 3.15 4.2 Max 0.5 1.35 1.8 V V V V V V 3.98 4.32 5.48 5.81 0.15 0.26 0.16 0.26 3.5 ±0.1 ±0.5 8 - supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V input capacitance 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 5 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit see Figure 8. Symbol Parameter Conditions Min tpd propagation delay nl0, nI1to nY; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF S to nY; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF ten enable time OE to nY; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tdis disable time OE to nY; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tt transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance per multiplexer; VI = GND to VCC [5] [4] [3] [2] [1] 25 °C Typ Max −40 °C to +125 °C Unit Max (85 °C) 120 24 20 175 35 30 175 35 30 190 38 33 75 15 13 Max (125 °C) 145 29 25 210 42 36 210 42 36 225 45 38 90 18 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF - 30 11 9 9 47 17 14 14 39 14 11 55 20 16 14 5 4 55 95 19 16 140 28 24 140 28 24 150 30 26 60 12 10 - [1] [2] [3] [4] [5] tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 6 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 11. Waveforms VI S, nI0, nI1 input GND tPHL VOH nY output VOL tTHL tTLH 001aab970 VM tPLH VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Input (nI0, nI1 and S) to output (nY) propagation delays and output transition times tr VI OE input GND tPLZ output LOW to OFF OFF to LOW VCC VX tPHZ VY VM tf tPZL VM tPZH VM VOL VOH output HIGH to OFF OFF to HIGH GND outputs enabled outputs disabled outputs enabled 001aab971 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 8. Input VM 0.5 × VCC Enable and disable times Measurement points Output VM 0.5 × VCC VX 0.1 × VCC VY 0.9 × VCC 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 7 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Table 9. VCC 2.0 V 4.5 V 6.0 V 5.0 V Test circuit for measuring switching times Test data Input VI VCC VCC VCC VCC tr = tf 6 ns 6 ns 6 ns 6 ns Load CL 50 pF 50 pF 50 pF 15 pF RL 1 kΩ 1 kΩ 1 kΩ 1 kΩ S1 tPZL, tPLZ VCC VCC VCC VCC tPZH, tPHZ GND GND GND GND tPHL, tPLH open open open open Supply voltage 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 8 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 9. 74HC258_4 Package outline SOT38-4 (DIP16) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 9 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 10 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT338-1 (SSOP16) 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 11 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20080414 Data sheet status Product data sheet Change notice Supersedes 74HC258_3 Document ID 74HC258_4 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Pin assignment corrected for pins 10, 11, 13 and 14 in Figure 1, Figure 2, Figure 5 and Table 2. Product data sheet Product specification Product specification 74HC_HCT258_CNV_2 74HC_HCT258_1 - 74HC258_3 74HC_HCT258_CNV_2 74HC_HCT258_1 20041112 19990902 19901201 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 12 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC258_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 14 April 2008 13 of 14 NXP Semiconductors 74HC258 Quad 2-input multiplexer; 3-state; inverting 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 April 2008 Document identifier: 74HC258_4