74HC299D

74HC299; 74HCT299 8-bit universal shift register; 3-state Rev. 03 — 28 July 2008 Product data sheet 1. General description The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified in compliance with JEDEC standard no. 7A. The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. An operation is determined by the mode select inputs S0 and S1, as shown in Table 3. Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is in either state, provided that the recommended set-up and hold times are observed. A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations still occur when preparing for a parallel load operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1. 2. Features I Multiplexed inputs/outputs provide improved bit density I Four operating modes: N Shift left N Shift right N Hold (store) N Load data I Operates with output enable or at high-impedance OFF-state (Z) I 3-state outputs drive bus lines directly I Cascadable for n-bit word lengths I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and from −40 °C to +125 °C NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range 74HC299 74HC299D 74HC299DB 74HC299N 74HC299PW 74HCT299 74HCT299D 74HCT299DB 74HCT299N 74HCT299PW −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO20 SSOP20 DIP20 TSSOP20 plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm plastic dual in-line package; 20 leads (300 mil) SOT163-1 SOT339-1 SOT146-1 −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO20 SSOP20 DIP20 TSSOP20 plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm plastic dual in-line package; 20 leads (300 mil) SOT163-1 SOT339-1 SOT146-1 Name Description Version Type number plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 4. Functional diagram 1 DSR CP MR Q0 OE1 OE2 INPUT/3-STATE OUTPUT CIRCUITRY I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 7 13 6 14 5 15 4 16 001aai460 19 S0 S1 DSL 11 12 9 8 2 3 18 8-BIT SHIFT REGISTER Q7 17 Fig 1. Functional diagram 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 2 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 9 2 3 1 19 12 11 7 13 6 14 5 15 4 16 18 R & SRG8 3EN5 0 0 M 3 1 C4/1 /2 1, 4D 3, 4D 6, 5 3, 4D 5 1 19 11 18 S0 S1 DSR DSL I/O0 I/O1 I/O2 I/O3 I/O4 7 13 6 14 5 15 4 16 8 17 Z6 8 12 9 2 3 CP MR I/O5 I/O6 I/O7 OE Q0 Q7 3, 4D 7, 5 2, 4D Z7 17 001aai458 001aai459 Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 3 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state DSR S0 S1 D Q CP FF0 RD I/O0 CP Q0 D Q CP FF1 RD I/O1 OE1 OE2 D Q CP FF2 RD I/O2 D Q CP FF3 RD I/O3 D Q CP FF4 RD I/O4 D Q CP FF5 RD I/O5 D Q CP FF6 RD I/O6 DSL D Q CP FF7 RD I/O7 Q7 MR 001aai461 Fig 4. Logic diagram 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 4 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 5. Pinning information 5.1 Pinning 74HC299 74HCT299 S0 1 2 3 4 5 6 7 8 9 20 VCC 19 S1 18 DSL 17 Q7 16 I/O7 15 I/O5 14 I/O3 13 I/O1 12 CP 11 DSR 001aai457 74HC299 74HCT299 S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR 1 2 3 4 5 6 7 8 9 20 VCC 19 S1 18 DSL 17 Q7 16 I/O7 15 I/O5 14 I/O3 13 I/O1 12 CP 11 DSR 001aai511 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR GND 10 GND 10 Fig 5. Pin configuration (SO20 and (T)SSOP20) Fig 6. Pin configuration (DIP20) 5.2 Pin description Table 2. Symbol S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR GND DSR CP I/O1 I/O3 I/O5 I/O7 Q7 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description mode select input 3-state output enable input (active LOW) 3-state output enable input (active LOW) parallel data input or 3-state parallel output (bus driver) parallel data input or 3-state parallel output (bus driver) parallel data input or 3-state parallel output (bus driver) parallel data input or 3-state parallel output (bus driver) serial output (standard output) asynchronous master reset input (active LOW) ground (0 V) serial data shift-right input clock input (LOW to HIGH, edge-triggered) parallel data input or 3-state parallel output (bus driver) parallel data input or 3-state parallel output (bus driver) parallel data input or 3-state parallel output (bus driver) parallel data input or 3-state parallel output (bus driver) serial output (standard output) 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 5 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Table 2. Symbol DSL S1 VCC Pin description …continued Pin 18 19 20 Description serial data shift-left input mode select input positive supply voltage 6. Functional description Table 3. Input MR L H H H H [1] Function table[1] Response S1 X H L H L S0 X H H L L CP X ↑ ↑ ↑ X asynchronous reset; Q0 to Q7 = LOW parallel load; I/On → Qn shift right; DSR → Q0, Q0 → Q1, etc. shift left; DSL → Q7, Q7 → Q6, etc. hold H = HIGH voltage level; L = LOW voltage level; ↑ = LOW to HIGH CP transition; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO Parameter supply voltage input clamping current output clamping current output current standard outputs bus driver outputs ICC supply current standard outputs bus driver outputs IGND ground current standard outputs bus driver outputs Tstg Ptot storage temperature total power dissipation Tamb = −40 °C to +125 °C DIP20 package SO20 package (T)SSOP20 package [1] [2] [3] [4] Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V −0.5 V < VO < VCC + 0.5 V [1] [1] Min −0.5 −50 −70 −65 - Max +7 ±20 ±20 ±25 ±35 50 70 +150 750 500 500 Unit V mA mA mA mA mA mA mA mA °C mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. © NXP B.V. 2008. All rights reserved. 74HC_HCT299_3 Product data sheet Rev. 03 — 28 July 2008 6 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state [2] [3] [4] Ptot derates linearly at 12 mW/K above 70 °C. Ptot derates linearly at 8 mW/K above 70 °C. Ptot derates linearly at 5.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO Tamb ∆t/∆V Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1.67 625 139 83 1.67 1.39 ns/V ns/V ns/V Conditions 74HC299 Min 2.0 0 0 −40 Typ 5.0 Max 6.0 VCC VCC 74HCT299 Min 4.5 0 0 Typ 5.0 Max 5.5 VCC VCC V V V Unit +125 −40 +125 °C 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min 74HC299 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1.5 3.15 4.2 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V 25 °C Typ Max −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 7 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V standard outputs IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V bus driver outputs IO = −6.0 mA; VCC = 4.5 V IO = −7.8 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V standard outputs IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V bus driver outputs IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V II IOZ ICC CI CI/O CPD input leakage current OFF-state output current supply current input capacitance input/output capacitance power dissipation capacitance HIGH-level input voltage per package [1] 25 °C Typ Max −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 - 1.9 4.4 5.9 3.84 5.34 - 1.9 4.4 5.9 3.7 5.2 - V V V V V 3.98 5.48 4.32 5.81 - 3.84 5.34 - 3.7 5.2 - V V - 0 0 0 0.15 0.16 0.15 0.16 3.5 10 120 0.1 0.1 0.1 0.26 0.26 0.26 0.26 ±0.1 ±0.5 8.0 - - 0.1 0.1 0.1 0.33 0.33 0.33 0.33 ±1.0 ±5.0 80 - - 0.1 0.1 0.1 0.4 0.4 0.4 0.4 ±1.0 V V V V V V V µA VI = VCC or GND; VCC = 6.0 V VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V ±10.0 µA 160 µA pF pF pF 74HCT299 VIH VCC = 4.5 V to 5.5 V 2.0 1.6 2.0 2.0 V 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 8 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VIL VOH LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VI = VIH or VIL; VCC = 4.5 V all outputs IO = −20 µA standard outputs IO = −4.0 mA bus driver outputs IO = −6.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V all outputs IO = 20 µA standard outputs IO = 4.0 mA bus driver outputs IO = 6.0 mA II IOZ input leakage current OFF-state output current VI = VCC or GND; VCC = 5.5 V VI = VIH or VIL; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input pin; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V I/On, DSR, DSL, MR and S1 CP, S0 OEn CI CI/O CPD input capacitance input/output capacitance power dissipation capacitance per package [1] 25 °C Typ 1.2 Max 0.8 −40 °C to +85 °C Min Max 0.8 −40 °C to +125 °C Min Max 0.8 Unit - V 4.4 3.98 3.98 4.5 4.32 4.32 - 4.4 3.84 3.84 - 4.4 3.7 3.7 - V V V - 0 0.15 0.16 - 0.1 0.26 0.26 ±0.1 ±0.5 - 0.1 0.33 0.33 ±1.0 ±5.0 - 0.1 0.4 0.4 ±1.0 V V V µA ±10.0 µA ICC ∆ICC supply current additional supply current - - 8.0 - 80 - 160 µA - 25 60 30 3.5 10 125 90 216 108 - - 112.5 270 135 - - 122.5 µA 294 147 µA µA pF pF pF [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; © NXP B.V. 2008. All rights reserved. 74HC_HCT299_3 Product data sheet Rev. 03 — 28 July 2008 9 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state ∑(CL × VCC2 × fo) = sum of outputs. CL = output load capacitance in pF; VCC = supply voltage in V; VI = GND to VCC for 74HC299; VI = GND to (VCC − 1.5 V) for 74HCT299. 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit, see Figure 11. Symbol Parameter Conditions Min 74HC299 tpd propagation delay CP to Q0, Q7; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CP to I/On; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V MR to Q0, Q7 or I/On; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tt transition time bus driver (I/On); see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V standard (Q0, Q7); see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 19 7 6 75 15 13 95 19 16 110 22 19 ns ns ns [3] [2] [1] 25 °C Typ Max −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit - 66 24 20 19 66 24 20 19 200 40 34 200 40 34 - 250 50 43 250 50 43 - 300 60 51 300 60 51 ns ns ns ns ns ns ns ns - 66 24 20 19 14 5 4 200 40 34 60 12 10 - 250 50 43 75 15 13 - 300 60 51 90 18 15 ns ns ns ns ns ns ns 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 10 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit, see Figure 11. Symbol Parameter Conditions Min tW pulse width CP HIGH or LOW; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR LOW; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPZH OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay recovery time OEn to I/On; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPZL OEn to I/On; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPHZ OEn to I/On; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPLZ OEn to I/On; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trec MR to CP; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 5 5 5 −14 −5 −4 5 5 5 5 5 5 ns ns ns 55 20 16 155 31 26 195 39 33 235 47 40 ns ns ns [5] [4] 25 °C Typ 17 6 5 19 7 6 50 18 14 41 15 12 66 24 19 Max 155 31 26 130 26 22 185 37 31 −40 °C to +85 °C Min 100 20 17 100 20 17 Max 195 39 33 165 33 28 230 46 39 −40 °C to +125 °C Min 120 24 20 120 24 20 Max 235 47 40 195 39 33 280 56 48 Unit 80 16 14 80 16 14 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 11 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit, see Figure 11. Symbol Parameter Conditions Min tsu set-up time DSR, DSL to CP; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V S0, S1 to CP; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V I/On to CP; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time I/On, DSR, DSL to CP; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V S0, S1 to CP; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum frequency CP input; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V 74HCT299 tpd propagation delay CP to Q0, Q7; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CP to I/On; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF MR to Q0, Q7 or I/On; see Figure 8 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF [2] [1] 25 °C Typ 33 12 10 33 12 10 39 14 11 Max - −40 °C to +85 °C Min 125 25 21 125 25 21 155 31 26 Max - −40 °C to +125 °C Min 150 30 26 150 30 26 190 38 32 Max - Unit 100 20 17 100 20 17 125 25 21 ns ns ns ns ns ns ns ns ns 0 0 0 0 0 0 5.0 25 29 −14 −5 −4 −28 −10 −8 15 45 50 54 - 0 0 0 0 0 0 4.0 20 24 - 0 0 0 0 0 0 3.4 17 20 - ns ns ns ns ns ns MHz MHz MHz MHz - 22 19 22 19 37 37 - - 46 46 - - 56 56 - ns ns ns ns - 27 23 46 - - 58 - - 69 - ns ns 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 12 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit, see Figure 11. Symbol Parameter Conditions Min tt transition time bus driver (I/On); see Figure 7 VCC = 4.5 V standard (Q0, Q7); see Figure 7 VCC = 4.5 V tW pulse width clock HIGH or LOW; see Figure 7 VCC = 4.5 V master reset LOW; see Figure 8 VCC = 4.5 V ten tPHZ enable time HIGH to OFF-state propagation delay LOW to OFF-state propagation delay recovery time set-up time OEn to I/On; see Figure 10 VCC = 4.5 V OEn to I/On; see Figure 10 VCC = 4.5 V [5] [4] [3] 25 °C Typ 5 7 10 11 19 24 Max 12 15 30 37 −40 °C to +85 °C Min 25 25 Max 15 19 38 46 −40 °C to +125 °C Min 30 30 Max 18 22 45 56 Unit 20 20 - ns ns ns ns ns ns tPLZ OEn to I/On; see Figure 10 VCC = 4.5 V 20 32 40 48 ns trec tsu MR to CP; see Figure 8 VCC = 4.5 V I/On, DSR, DSL to CP; see Figure 7 VCC = 4.5 V S0, S1 to CP; see Figure 9 VCC = 4.5 V 32 18 40 48 ns 25 14 31 38 ns 10 2 9 11 ns th hold time I/On, DSR, DSL to CP; see Figure 7 VCC = 4.5 V S0, S1 to CP; see Figure 9 VCC = 4.5 V 0 25 −17 42 46 0 20 0 17 ns MHz MHz 0 −11 0 0 ns fmax maximum frequency CP input; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF [1] [2] [3] [4] [5] tpd is the same as tPHL and tPLH. tpd is the same as tPHL. tt is the same as tTHL and tTLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 13 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state [6] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; Σ(CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching. 11. Waveforms VI I/On, DSR, DSL inputs GND VM th tsu 1/fmax VI CP input GND VM th tsu tW tPHL VOH I/On, Q0, Q7 outputs VOL VM tPLH tTHL tTLH 001aai462 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Clock pulse to outputs I/On, Q0, Q7 propagation delays, the clock pulse width, the I/On, DSR and DSL to clock pulse set-up and hold times, the output transition times and the maximum clock frequency 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 14 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state VI MR input GND tW trec VI CP input GND tPHL VOH I/On, Q0, Q7 outputs VOL VM 001aai463 VM VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and the master reset to clock pulse removal time VI I/On, DSR, DSL, Sn inputs GND tsu VI CP input GND VM 001aai464 VM th tsu th Measurement points are given in Table 8. Fig 9. Set-up and hold times from the mode control inputs S0, S1 to the clock pulse 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 15 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state tr VI OEn input GND 10 % tPLZ VOH I/On output LOW to OFF OFF to LOW VOL tPHZ VOH I/On output HIGH to OFF OFF to HIGH VOL outputs enabled 90 % 90 % VM tf tPZL VM 10 % tPZH VM outputs disabled outputs enabled 001aai465 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10. 3-state enable and disable times for OEn inputs Table 8. Type 74HC299 74HCT299 Measurement points Input VI VCC 3V VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V VCC VI VO RL = 1 kΩ CL 50 pF VCC PULSE GENERATOR S1 DUT RT open 001aai466 Test data is given in Table 9. Definitions for test circuit: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 11. Test circuit for measuring switching times 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 16 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state Table 9. Type 74HC299 74HCT299 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 17 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT163-1 (SO20) 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 18 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 10 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT339-1 (SSOP20) 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 19 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 D seating plane ME A2 A L A1 c Z e b1 b 20 11 MH wM (e 1) pin 1 index E 1 10 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) E (1) e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2 0.078 26.92 26.54 1.060 1.045 6.40 6.22 0.25 0.24 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC MS-001 JEITA SC-603 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 14. Package outline SOT146-1 (DIP20) 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 20 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT360-1 (TSSOP20) 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 21 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 13. Revision history Table 10. Revision history Release date 20080728 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT299_CNV_2 Document ID 74HC_HCT299_3 Modifications: • • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: Ordering information added Section 12: Package outline drawings added Section 9 “Static characteristics”: Family data added Section 11 “Waveforms”: Test circuit added Product specification - 74HC_HCT299_CNV_2 19970828 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 22 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 14. Legal information 14.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT299_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 28 July 2008 23 of 24 NXP Semiconductors 74HC299; 74HCT299 8-bit universal shift register; 3-state 16. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 July 2008 Document identifier: 74HC_HCT299_3