74HC2G66

74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch Rev. 06 — 2 April 2010 Product data sheet 1. General description 74HC2G66 and 74HCT2G66 are high-speed Si-gate CMOS devices. They are dual single-pole single-throw analog switches. Each switch has two input/output pins (nY and nZ) and an active HIGH enable input pin (nE). When pin nE is LOW, the analog switch is turned off. 2. Features and benefits Wide supply voltage range from 2.0 V to 10.0 V for 74HC2G66 Very low ON resistance: 41 Ω (typ.) at VCC = 4.5 V 30 Ω (typ.) at VCC = 6.0 V 21 Ω (typ.) at VCC = 9.0 V High noise immunity Low power dissipation 25 mA continuous switch current Multiple package options ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74HC2G66DP 74HCT2G66DP 74HC2G66DC 74HCT2G66DC 74HC2G66GD 74HCT2G66GD −40 °C to +125 °C XSON8U −40 °C to +125 °C VSSOP8 −40 °C to +125 °C Name TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number plastic very thin shrink small outline package; 8 SOT765-1 leads; body width 2.3 mm plastic extremely thin small outline package; no SOT996-2 leads; 8 terminals; UTLP based; body 3 × 2 × 0.5 mm NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 4. Marking Table 2. Marking codes Marking H66 T66 H66 T66 H66 T66 Type number 74HC2G66DP 74HCT2G66DP 74HC2G66DC 74HCT2G66DC 74HC2G66GD 74HCT2G66GD 5. Functional diagram 1Y 1Z 1E 2Z 2Y Y Z 2E E 001aag497 001aah372 Fig 1. Logic symbol Fig 2. Logic diagram for 1 switch 6. Pinning information 6.1 Pinning 74HC2G66 74HCT2G66 1Y 1 2 3 4 8 7 6 5 VCC 1E 2Z 2Y 74HC2G66 74HCT2G66 1Y 1Z 2E GND 1 2 3 4 001aai699 1Z 8 7 6 5 VCC 1E 2Z 2Y 2E GND 001aal625 Transparent top view Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT996-2 (XSON8U) 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 2 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 6.2 Pin description Table 3. Symbol 1Y, 2Y 1Z, 2Z GND 1E, 2E VCC Pin description Pin 1, 5 2, 6 4 7, 3 8 Description independent input or output independent input or output ground (0 V) enable input (active HIGH) supply voltage 7. Functional description Table 4. Input nE L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Switch OFF ON 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK ISK ISW ICC IGND Tstg Ptot Parameter supply voltage input clamping current switch clamping current switch current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C per package per switch [1] [2] [2] [2] Conditions VI < −0.5 V or VI > VCC + 0.5 V VI < −0.5 V or VI > VCC + 0.5 V VSW > −0.5 V or VSW < VCC + 0.5 V [1] [1] Min −0.5 −30 −65 - Max +11.0 ±20 ±20 ±20 30 +150 300 100 Unit V mA mA mA mA mA °C mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 packages above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 3 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V).[1] Symbol Parameter VCC VI VO VSW Tamb Δt/ΔV supply voltage input voltage output voltage switch voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 10.0 V [1] Conditions Min 2.0 0 0 0 −40 - 74HC2G66 Typ 5.0 +25 1.67 Max 10.0 VCC VCC VCC +125 625 139 83 35 Min 4.5 0 0 0 −40 - 74HCT2G66 Typ 5.0 +25 1.67 Max 5.5 VCC VCC VCC +125 139 - Unit V V V V °C ns/V ns/V ns/V ns/V To avoid drawing VCC current out of pin nZ, when switch current flows in pin nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into pin nZ, no VCC current will flow out of terminal nY. In this case there is no limit for the voltage drop across the switch, but the voltage at pins nY and nZ may not exceed VCC or GND. 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC2G66 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V II input leakage current nE; VI = VCC or GND VCC = 6.0 V VCC = 9.0 V IS(OFF) IS(ON) ICC OFF-state leakage current ON-state leakage current supply current nY or nZ; VCC = 9.0 V; see Figure 5 nY or nZ; VCC = 9.0 V; see Figure 6 nE, nY and nZ = VCC or GND VCC = 6.0 V VCC = 9.0 V 74HC_HCT2G66_6 Conditions −40 °C to +85 °C Min 1.5 3.15 4.2 6.3 Typ[1] 1.2 2.4 3.2 4.7 0.8 2.1 2.8 4.3 0.1 0.1 Max 0.5 1.35 1.8 2.7 ±0.1 ±0.2 1.0 1.0 −40 °C to +125 °C Unit Min 1.5 3.15 4.2 6.3 Max 0.5 1.35 1.8 2.7 ±0.1 ±0.2 1.0 1.0 V V V V V V V V μA μA μA μA - - 10 20 - 20 40 μA μA All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 4 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter CI CPD CS(ON) VIH VIL II IS(OFF) IS(ON) ICC ΔICC CI CPD CS(ON) [1] Conditions −40 °C to +85 °C Min Typ[1] 3.5 9 8 1.6 1.2 0.1 0.1 3.5 9 8 Max 0.8 ±1.0 1.0 1.0 10 375 - −40 °C to +125 °C Unit Min 2.0 Max 0.8 ±1.0 1.0 1.0 20 410 pF pF pF V V μA μA μA μA μA pF pF pF input capacitance power dissipation capacitance ON-state capacitance HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current ON-state leakage current supply current additional supply current input capacitance power dissipation capacitance ON-state capacitance VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V nE; VI = VCC or GND; VCC = 5.5 V nY or nZ; VCC = 5.5 V; see Figure 5 nY or nZ; VCC = 5.5 V; see Figure 6 nE, nY and nZ = VCC or GND; VCC = 4.5 V to 5.5 V nE = VCC − 2.1 V; IO = 0 A; VCC = 4.5 V to 5.5 V; 74HCT2G66 2.0 - Typical values are measured at Tamb = 25 °C. 10.1 Test circuits VCC VIL IS VI VCC VIH nZ IS VO VI nE nY GND nE nY GND nZ IS VO 001aaj465 001aaj466 VI = VCC or GND and VO = GND or VCC. VI = VCC or GND and VO = open circuit. Fig 5. Test circuit for measuring OFF-state leakage current Fig 6. Test circuit for measuring ON-state leakage current 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 5 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 10.2 ON resistance Table 8. ON resistance for 74HC2G66 and 74HCT2G66 At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graph see Figure 8. Symbol Parameter Conditions −40 °C to +85 °C Min 74HC2G66[1] RON(peak) ON resistance (peak) VI = GND to VCC; see Figure 7 and 8 ISW = 0.1 mA; VCC = 2.0 V ISW = 1.0 mA; VCC = 4.5 V ISW = 1.0 mA; VCC = 6.0 V ISW = 1.0 mA; VCC = 9.0 V RON(rail) ON resistance (rail) VI = GND; see Figure 7 and 8 ISW = 0.1 mA; VCC = 2.0 V ISW = 1.0 mA; VCC = 4.5 V ISW = 1.0 mA; VCC = 6.0 V ISW = 1.0 mA; VCC = 9.0 V VI = VCC; see Figure 7 and 8 ISW = 0.1 mA; VCC = 2.0 V ISW = 1.0 mA; VCC = 4.5 V ISW = 1.0 mA; VCC = 6.0 V ISW = 1.0 mA; VCC = 9.0 V ΔRON ON resistance mismatch between channels VI = VCC to GND; see Figure 7 and 8 VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V 74HCT2G66 RON(peak) ON resistance (peak) RON(rail) ON resistance (rail) VI = GND to VCC; see Figure 7 and 8 ISW = 1.0 mA; VCC = 4.5 V VI = GND; see Figure 7 and 8 ISW = 1.0 mA; VCC = 4.5 V VI = VCC; see Figure 7 and 8 ISW = 1.0 mA; VCC = 4.5 V ΔRON ON resistance mismatch between channels VI = VCC to GND; see Figure 7 and 8 VCC = 4.5 V 5 Ω 31 106 128 Ω 28 95 115 Ω 41 118 142 Ω 5 4 3 Ω Ω Ω 65 31 23 19 106 94 78 128 113 95 Ω Ω Ω Ω 65 28 22 18 95 82 70 115 100 80 Ω Ω Ω Ω 250 41 30 21 118 105 88 142 126 105 Ω Ω Ω Ω Typ[2] Max −40 °C to +125 °C Min Max Unit [1] [2] At supply voltages approaching 2 V, the ON resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using this supply voltage. Typical values are measured at Tamb = 25 °C. 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 6 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 10.3 ON resistance test circuit and graphs 60 VSW VCC VIH nE nY GND nZ 20 VCC = 9.0 V ISW mnb006 RON (Ω) VCC = 4.5 V 40 VCC = 6.0 V VI 0 0 001aaj467 2 4 6 8 VI (V) 10 RON = VSW / ISW. Tamb = 25 °C. Fig 7. Test circuit for measuring ON resistance Fig 8. Typical ON resistance as a function of input voltage 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 11. Symbol Parameter 74HC2G66 tpd propagation delay nY to nZ or nZ to nY; RL = ∞ Ω; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V ten enable time nE to nY or nZ; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V tdis disable time nE to nY or nZ; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V CPD power dissipation VI = GND to VCC capacitance [3] [2] [2] [2] Conditions −40 °C to +85 °C Min Typ[1] Max −40 °C to +125 °C Unit Min Max - 6.5 2 1.5 1.2 40 12 10 7 21 12 11 10 9 65 13 11 10 125 29 21 16 145 29 28 23 - - 80 15 14 12 150 30 26 20 175 35 33 27 - ns ns ns ns ns ns ns ns ns ns ns ns pF 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 7 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 11. Symbol Parameter 74HCT2G66 tpd propagation delay nY to nZ or nZ to nY; RL = ∞ Ω; see Figure 9 VCC = 4.5 V ten tdis CPD enable time disable time nE to nY or nZ; see Figure 10 VCC = 4.5 V nE to nY or nZ; see Figure 10 VCC = 4.5 V power dissipation VI = GND to VCC − 1.5 V capacitance All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] CPD is used to determine the dynamic power dissipation PD (μW). PD = CPD × VCC2 × fi + Σ((CL × CSW) × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CSW = maximum switch capacitance in pF (see Table 7); VCC = supply voltage in volts; Σ((CL × CSW) × VCC2 × fo) = sum of outputs. [3] [2] [2] [2] Conditions −40 °C to +85 °C Min Typ[1] Max −40 °C to +125 °C Unit Min Max - 2 13 13 9 15 30 44 - - 18 36 53 - ns ns ns pF [1] [2] 11.1 Waveforms and test circuit VI nY or nZ input GND t PLH VOH nZ or nY output VOL 001aaa541 VM VM t PHL VM VM Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Input (nY or nZ) to output (nZ or nY) propagation delays 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 8 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch VI nE input GND t PLZ VCC nY or nZ output LOW-to-OFF OFF-to-LOW VOL t PHZ output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND switch enabled switch disabled switch enabled 001aaa542 VM t PZL VM VX t PZH nY or nZ Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Enable and disable times Table 10. Type 74HC2G66 74HCT2G66 Measurement points Input VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V VX VOL + 10 % VOL + 10 % VY VOH − 10 % VOH − 10 % 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 9 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 11. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 11. Test circuit for measuring switching times Table 11. Type 74HC2G66 74HCT2G66 [1] Test data Input VI GND to VCC GND to 3 V tr, tf [1] Load CL 50 pF 50 pF RL 1 kΩ 1 kΩ 6 ns 6 ns S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC There is no constraint on tr, tf with a 50 % duty factor when measuring fmax. 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics for 74HC2G66 and 74HCT2G66 GND = 0 V; tr = tf = 6.0 ns; CL = 50 pF; unless otherwise specified. All typical values are measured at Tamb = 25 °C. Symbol THD Parameter total harmonic distortion Conditions fi = 1 kHz; RL = 10 kΩ; see Figure 12 VCC = 4.5 V; VI = 4.0 V (p-p) VCC = 9.0 V; VI = 8.0 V (p-p) fi = 10 kHz; RL = 10 kΩ; see Figure 12 VCC = 4.5 V; VI = 4.0 V (p-p) VCC = 9.0 V; VI = 8.0 V (p-p) 0.12 0.06 % % 0.04 0.02 Min Typ Max Unit % % % 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 10 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch Table 12. Additional dynamic characteristics for 74HC2G66 and 74HCT2G66 …continued GND = 0 V; tr = tf = 6.0 ns; CL = 50 pF; unless otherwise specified. All typical values are measured at Tamb = 25 °C. Symbol f(−3dB) Parameter −3 dB frequency response Conditions RL = 50 Ω; CL = 10 pF; see Figure 13 and 14 VCC = 4.5 V VCC = 9.0 V αiso isolation (OFF-state) RL = 600 Ω; fi = 1 MHz; see Figure 15 and 16 VCC = 4.5 V VCC = 9.0 V Vct crosstalk voltage between digital input and switch (peak to peak value); RL = 600 Ω; fi = 1 MHz; see Figure 17 VCC = 4.5 V VCC = 9.0 V Xtalk crosstalk between switches; RL = 600 Ω; fi = 1 MHz; see Figure 18 VCC = 4.5 V VCC = 9.0 V −60 −60 dB dB 110 220 mV mV −50 −50 dB dB 180 200 MHz MHz Min Typ Max Unit 11.3 Test circuits and graphs VCC VIH 10 μF VCC VIH 0.1 μF VCC nE VCC nE 2RL 2RL nY/nZ nZ/nY VO 2RL CL nY/nZ nZ/nY VO 2RL CL fi D fi dB 001aaj468 001aaj469 With fi = 1 MHz adjust the switch input voltage for a 0 dBm level at the switch output, (0 dBm = 1 mW into 50 Ω). Then Increase the input frequency until the dB meter reads −3 dB. Fig 12. Test circuit for measuring total harmonic distortion Fig 13. Test circuit for measuring the −3 dB frequency response 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 11 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 5 mna083 (dB) 0 −5 10 102 103 104 105 fi (kHz) 106 Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; RSOURCE = 1 kΩ. Fig 14. Typical −3 dB frequency response VCC VIL 0.1 μF VCC nE 2RL nY/nZ nZ/nY VO CL 2RL fi dB 001aaj470 Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 Ω) Fig 15. Test circuit for measuring isolation (OFF-state) 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 12 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 0 (dB) −20 mna082 −40 −60 −80 −100 10 102 103 104 105 fi (kHz) 106 Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; RSOURCE = 1 kΩ. Fig 16. Typical isolation (OFF-state) as a function of frequency VCC 2RL nE VCC GND VCC 2RL nY/nZ DUT 2RL 2RL CL nZ/nY oscilloscope GND mnb011 a. Circuit V(p−p) mnb012 b. Crosstalk voltage Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 Ω) Fig 17. Test circuit for measuring crosstalk voltage (between the digital input and the switch) 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 13 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch VCC VIH 0.1 μF RL 1E 1Y or 1Z CHANNEL ON 1Z or 1Y 2RL fi 2RL CL V VO1 VIL VCC 2RL 2E VCC 2RL 2Y or 2Z CHANNEL OFF 2Z or 2Y V 2RL 2RL CL VO2 001aai846 Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 Ω) Fig 18. Test circuit for measuring crosstalk (between the switches) 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 14 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 19. Package outline SOT505-2 (TSSOP8) 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 15 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 20. Package outline SOT765-1 (VSSOP8) 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 16 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 21. Package outline SOT996-2 (XSON8U) 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 17 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 13. Abbreviations Table 13. Acronym CMOS ESD HBM MM TTL DUT Abbreviations Description Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic Device Under Test 14. Revision history Table 14. Revision history Release date 20100402 Data sheet status Product data sheet Product data sheet Change notice Supersedes 74HC_HCT2G66_5 74HC_HCT2G66_4 Document ID 74HC_HCT2G66_6 Modifications: 74HC_HCT2G66_5 Modifications: • • • • • • Added type number 74HC2G66GD and 74HCT2G66GD (XSON8U package) The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 1 “Ordering information” and Section 12 “Package outline” package SOT765-1 added. Quick Reference Data and Soldering sections removed. Section 2 “Features and benefits” updated. Product specification Product specification Product specification Product specification 74HC_HCT2G66_3 74HC_HCT2G66_2 74HC_HCT2G66_1 - 20090126 74HC_HCT2G66_4 74HC_HCT2G66_3 74HC_HCT2G66_2 74HC_HCT2G66_1 20040519 20031126 20030808 20030625 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 18 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74HC_HCT2G66_6 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 19 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT2G66_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 April 2010 20 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms and test circuit . . . . . . . . . . . . . . . . 8 Additional dynamic characteristics . . . . . . . . . 10 Test circuits and graphs . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 April 2010 Document identifier: 74HC_HCT2G66_6