74HC4052DB,118

74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Rev. 10 — 19 July 2012 Product data sheet 1. General description The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A. The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The common channel select logics include two digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 and S1. VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E). The VCC to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the 74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC  VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). 2. Features and benefits  Wide analog input voltage range from 5 V to +5 V  Low ON resistance:  80  (typical) at VCC  VEE = 4.5 V  70  (typical) at VCC  VEE = 6.0 V  60  (typical) at VCC  VEE = 9.0 V  Logic level translation: to enable 5 V logic to communicate with 5 V analog signals  Typical ‘break before make’ built-in  Complies with JEDEC standard no. 7A  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Specified from 40 C to +85 C and 40 C to +125 C 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 3. Applications  Analog multiplexing and demultiplexing  Digital multiplexing and demultiplexing  Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4052N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HC4052D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC4052DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC4052PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HC4052BQ 40 C to +125 C DHVQFN16 plastic dual-in line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm SOT763-1 74HCT4052N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT4052D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT4052DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 DHVQFN16 plastic dual-in line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm SOT763-1 74HC4052 74HCT4052 74HCT4052PW 40 C to +125 C 74HCT4052BQ 74HC_HCT4052 Product data sheet 40 C to +125 C All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 2 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 5. Functional diagram 10 13 1Z 1Y0 12 10 S0 1Y1 14 9 S1 1Y2 15 6 E 1Y3 11 2Y0 1 2Y1 5 2Y2 2 2Y3 4 0 4× 9 1 6 G4 0 3 MDX 3 0 1 1 5 2 2 3 4 12 14 13 15 2Z 11 001aah824 3 Fig 1. 001aah825 Logic symbol Fig 2. IEC logic symbol nYn VCC VEE VCC VCC VCC VEE from logic VEE nZ mnb043 Fig 3. Schematic diagram (one switch) 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 3 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer VDD 16 13 12 14 15 S0 10 11 S1 E 9 LOGIC LEVEL CONVERSION 1Y0 1Y1 1Y2 1Y3 1-OF-4 DECODER 1 2Y0 6 5 2 4 3 Fig 4. 1Z 8 7 VSS VEE 2Y1 2Y2 2Y3 2Z 001aah872 Functional diagram 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 4 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 74HC4052 74HCT4052 16 VCC 2Y2 2 15 1Y2 2Z 3 14 1Y1 2Y3 4 2Y1 5 terminal 1 index area 16 VCC 1 1 2Y0 2Y0 74HC4052 74HCT4052 2Y2 2 15 1Y2 2Z 3 14 1Y1 13 1Z 2Y3 4 13 1Z 12 1Y0 2Y1 5 E 6 VEE 7 7 10 S0 GND 8 9 S1 11 1Y3 10 S0 9 VEE VCC S1 11 1Y3 8 6 GND E 12 1Y0 (1) 001aah823 Transparent top view 001aah822 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 5. Pin configuration for DIP16, SO16 and (T)SSOP16 Fig 6. Pin configuration for DHVQFN16 6.2 Pin description Table 2. Pin description Symbol Pin Description 2Y0 1 independent input or output 2Y0 2Y2 2 independent input or output 2Y2 2Z 3 common input or output 2 2Y3 4 independent input or output 2Y3 2Y1 5 independent input or output 2Y1 E 6 enable input (active LOW) VEE 7 negative supply voltage GND 8 ground (0 V) S1 9 select logic input 1 S0 10 select logic input 0 1Y3 11 independent input or output 1Y3 1Y0 12 independent input or output 1Y0 1Z 13 common input or output 1 1Y1 14 independent input or output 1Y1 1Y2 15 independent input or output 1Y2 VCC 16 positive supply voltage 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 5 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 7. Functional description 7.1 Function table Table 3. Function table[1] Input Channel on E S1 S0 L L L nY0 and nZ L L H nY1 and nZ L H L nY2 and nZ L H H nY3 and nZ H X X none [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VEE = GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions [1] Min Max Unit 0.5 +11.0 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA ISK switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V - 20 mA ISW switch current 0.5 V < VSW < VCC + 0.5 V - 25 mA IEE supply current - 20 mA ICC supply current - 50 mA IGND ground current - 50 mA Tstg storage temperature total power dissipation Ptot P [1] power dissipation 65 +150 C DIP16 package [2] - 750 mW SO16, (T)SSOP16, and DHVQFN16 package [3] - 500 mW - 100 mW per switch To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE. [2] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K. [3] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 6 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions supply voltage VCC 74HC4052 74HCT4052 Unit Min Typ Max Min Typ Max VCC  GND 2.0 5.0 10.0 4.5 5.0 5.5 V VCC  VEE 2.0 5.0 10.0 2.0 5.0 10.0 V - VCC GND - VCC V see Figure 7 and Figure 8 VI input voltage GND VSW switch voltage VEE - VCC VEE - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V VCC = 10.0 V - - 31 - - - ns/V mnb044 12 mnb045 12 VCC − GND (V) 10 VCC − GND (V) 8 8 operating area 6 operating area 4 4 2 0 0 4 8 0 12 0 VCC − VEE (V) Fig 7. Guaranteed operating area as a function of the supply voltages for 74HC4052 74HC_HCT4052 Product data sheet Fig 8. 4 8 VCC − VEE (V) 12 Guaranteed operating area as a function of the supply voltages for 74HCT4052 All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 7 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 10. Static characteristics Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4052: VCC  GND or VCC  VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4052: VCC  GND = 4.5 V and 5.5 V, VCC  VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter Tamb = 40 C to +85 Conditions Min Typ Max Unit - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - 100 225  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - 90 200  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - 70 165  - 150 -  - 80 175  C[1] RON(peak) ON resistance (peak) Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 A RON(rail) ON resistance (rail) [2] Vis = VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 A [2] VCC = 4.5 V; VEE = 0 V; ISW = 1000 A VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - 70 150  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - 60 130  - 150 -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - 90 200  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - 80 175  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - 65 150  Vis = VCC VCC = 2.0 V; VEE = 0 V; ISW = 100 A RON ON resistance mismatch between channels [2] Vis = VCC to VEE - - -  VCC = 4.5 V; VEE = 0 V - 9 -  VCC = 6.0 V; VEE = 0 V - 8 -  VCC = 4.5 V; VEE = 4.5 V - 6 -  - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 270  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 240  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 195  VCC = 2.0 V; VEE = 0 V [2] Tamb = 40 C to +125 C RON(peak) ON resistance (peak) Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 A 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 [2] © NXP B.V. 2012. All rights reserved. 8 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 …continued VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4052: VCC  GND or VCC  VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4052: VCC  GND = 4.5 V and 5.5 V, VCC  VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter Conditions Min Typ Max Unit RON(rail) ON resistance (rail) Vis = VEE - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 210  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 180  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 160  VCC = 2.0 V; VEE = 0 V; ISW = 100 A [2] Vis = VCC VCC = 2.0 V; VEE = 0 V; ISW = 100 A - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 240  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 210  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 180  [2] [1] All typical values are measured at Tamb = 25 C. [2] When supply voltages (VCC  VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of 2 V, it is recommended to use these devices only for transmitting digital signals. 001aai068 100 (1) RON (Ω) 80 60 (2) Vsw V (3) 40 VCC from select input Sn Vis 20 nZ nYn GND VEE Isw 0 0 1.8 3.6 Vis = 0 V to (VCC  VEE). 5.4 7.2 9.0 Vis (V) 001aah826 Vis = 0 V to (VCC  VEE). (1) VCC = 4.5 V V sw R ON = -------I sw (2) VCC = 6 V (3) VCC = 9 V Fig 9. Test circuit for measuring RON 74HC_HCT4052 Product data sheet Fig 10. Typical RON as a function of input voltage Vis All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 9 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 7. Static characteristics for 74HC4052 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Tamb = 40 C to +85 VIH VIL II IS(OFF) Conditions Min Typ Max Unit VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 9.0 V 6.3 4.7 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V VCC = 9.0 V - 4.3 2.7 V C[1] HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current VEE = 0 V; VI = VCC or GND VCC = 6.0 V - - 1.0 A VCC = 10.0 V - - 2.0 A VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 per channel - - 1.0 A all channels - - 2.0 A - - 2.0 A VCC = 6.0 V - - 80.0 A VCC = 10.0 V - - 160.0 A IS(ON) ON-state leakage current VI = VIH or VIL; VSW = VCC  VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE CI input capacitance Csw switch capacitance - 3.5 - pF independent pins nYn - 5 - pF common pins nZ - 12 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 9.0 V 6.3 - - V Tamb = 40 C to +125 C VIH VIL II HIGH-level input voltage LOW-level input voltage input leakage current 74HC_HCT4052 Product data sheet VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V VCC = 9.0 V - - 2.7 V VCC = 6.0 V - - 1.0 A VCC = 10.0 V - - 2.0 A VEE = 0 V; VI = VCC or GND All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 10 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 7. Static characteristics for 74HC4052 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 per channel - - 1.0 A all channels - - 2.0 A - - 2.0 A IS(ON) ON-state leakage current VI = VIH or VIL; VSW = VCC  VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE [1] VCC = 6.0 V - - 160.0 A VCC = 10.0 V - - 320.0 A Conditions Min Typ Max Unit All typical values are measured at Tamb = 25 C. Table 8. Static characteristics for 74HCT4052 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Tamb = 40 C to +85 C[1] VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V II input leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V - - 1.0 A IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 per channel - - 1.0 A all channels - - 2.0 A - - 2.0 A VCC = 5.5 V; VEE = 0 V - - 80.0 A VCC = 5.0 V; VEE = 5.0 V - - 160.0 A - 45 202.5 A - 3.5 - pF independent pins nYn - 5 - pF common pins nZ - 12 - pF VCC = 4.5 V to 5.5 V 2.0 - - V IS(ON) ON-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 12 ICC supply current VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE ICC additional supply current CI input capacitance Csw switch capacitance per input; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V Tamb = 40 C to +125 C VIH HIGH-level input voltage 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 11 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 8. Static characteristics for 74HCT4052 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V II input leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V - - 1.0 A IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 per channel - - 1.0 A all channels - - 2.0 A - - 2.0 A VCC = 5.5 V; VEE = 0 V - - 160.0 A VCC = 5.0 V; VEE = 5.0 V - - 320.0 A - - 220.5 A IS(ON) ON-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 12 ICC supply current VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE ICC [1] additional supply current per input; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V All typical values are measured at Tamb = 25 C. VCC from select input Sn Isw Isw Z Yn A GND Vis A VEE Vos 001aan383 Vis = VCC and Vos = VEE. Vis = VEE and Vos = VCC. Fig 11. Test circuit for measuring OFF-state current VCC HIGH from select input Sn Isw A Vis Z Yn GND Vos VEE 001aan384 Vis = VCC and Vos = open-circuit. Vis = VEE and Vos = open-circuit. Fig 12. Test circuit for measuring ON-state current 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 12 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 9. Dynamic characteristics for 74HC4052 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V; VEE = 0 V - 14 75 ns VCC = 4.5 V; VEE = 0 V - 5 15 ns VCC = 6.0 V; VEE = 0 V - 4 13 ns - 4 10 ns Tamb = 40 C to +85 C[1] tpd propagation delay Vis to Vos; RL =  ; see Figure 13 [2] VCC = 4.5 V; VEE = 4.5 V ton turn-on time E, Sn to Vos; RL =  ; see Figure 14 [3] VCC = 2.0 V; VEE = 0 V - 105 405 ns VCC = 4.5 V; VEE = 0 V - 38 81 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 28 - ns VCC = 6.0 V; VEE = 0 V - 30 69 ns - 26 58 ns VCC = 2.0 V; VEE = 0 V - 74 315 ns VCC = 4.5 V; VEE = 0 V - 27 63 ns VCC = 4.5 V; VEE = 4.5 V toff turn-off time E, Sn to Vos; RL = 1 k; see Figure 14 [4] VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 21 - ns VCC = 6.0 V; VEE = 0 V - 22 54 ns - 22 48 ns - 57 - pF VCC = 2.0 V; VEE = 0 V - - 90 ns VCC = 4.5 V; VEE = 0 V - - 18 ns VCC = 6.0 V; VEE = 0 V - - 15 ns - - 12 ns VCC = 4.5 V; VEE = 4.5 V CPD power dissipation per switch; VI = GND to VCC capacitance [5] Tamb = 40 C to +125 C tpd propagation delay Vis to Vos; RL =  ; see Figure 13 [2] VCC = 4.5 V; VEE = 4.5 V ton turn-on time 74HC_HCT4052 Product data sheet E, Sn to Vos; RL =  ; see Figure 14 [3] VCC = 2.0 V; VEE = 0 V - - 490 ns VCC = 4.5 V; VEE = 0 V - - 98 ns VCC = 6.0 V; VEE = 0 V - - 83 ns VCC = 4.5 V; VEE = 4.5 V - - 69 ns All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 13 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 9. Dynamic characteristics for 74HC4052 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol toff Parameter turn-off time Conditions Min Typ Max Unit VCC = 2.0 V; VEE = 0 V - - 375 ns VCC = 4.5 V; VEE = 0 V - - 75 ns VCC = 6.0 V; VEE = 0 V - - 64 ns VCC = 4.5 V; VEE = 4.5 V - - 57 ns Min Typ Max Unit - 5 15 ns - 4 10 ns VCC = 4.5 V; VEE = 0 V - 41 88 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 18 - ns - 28 60 ns VCC = 4.5 V; VEE = 0 V - 26 63 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 13 - ns - 21 48 ns - 57 - pF E, Sn to Vos; RL = 1 k; see Figure 14 [1] All typical values are measured at Tamb = 25 C. [2] tpd is the same as tPHL and tPLH. [3] ton is the same as tPZH and tPZL. [4] toff is the same as tPHZ and tPLZ. [5] [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + {(CL + Csw)  VCC2  fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; {(CL + Csw)  VCC2  fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. Table 10. Dynamic characteristics for 74HCT4052 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter Tamb = 40 C to +85 tpd Conditions C[1] propagation delay Vis to Vos; RL =  ; see Figure 13 [2] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V ton turn-on time E, Sn to Vos; RL = 1 k; see Figure 14 [3] VCC = 4.5 V; VEE = 4.5 V toff turn-off time E, Sn to Vos; RL = 1 k; see Figure 14 [4] VCC = 4.5 V; VEE = 4.5 V CPD power dissipation per switch; VI = GND to VCC  1.5 V capacitance 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 [5] © NXP B.V. 2012. All rights reserved. 14 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 10. Dynamic characteristics for 74HCT4052 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit - - 18 ns - - 12 ns - - 105 ns - - 72 ns Tamb = 40 C to +125 C propagation delay Vis to Vos; RL =  ; see Figure 13 tpd [2] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V turn-on time ton [3] E, Sn to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V turn-off time toff [1] [4] E, Sn to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V - - 75 ns VCC = 4.5 V; VEE = 4.5 V - - 57 ns All typical values are measured at Tamb = 25 C. [2] tpd is the same as tPHL and tPLH. [3] ton is the same as tPZH and tPZL. [4] toff is the same as tPHZ and tPLZ. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + {(CL + Csw)  VCC2  fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; {(CL + Csw)  VCC2  fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. Vis input 50 % tPLH Vos output tPHL 50 % 001aad555 Fig 13. Input (Vis) to output (Vos) propagation delays 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 15 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer VI VM E, Sn inputs 0V tPZL tPLZ 50 % Vos output 10 % tPHZ tPZH 90 % 50 % Vos output switch ON switch ON switch OFF 001aae330 For 74HC4052: VM = 0.5  VCC. For 74HCT4052: VM = 1.3 V. Fig 14. Turn-on and turn-off times VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC Vis PULSE GENERATOR VI VCC Vos RL S1 open DUT RT CL GND VEE 001aae382 Definitions for test circuit; see Table 11: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = Test selection switch. Fig 15. Test circuit for measuring AC performance 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 16 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 11. Test data Test Input VI Load Vis tr, tf S1 position CL RL at fmax other[1] tPHL, tPLH [2] pulse < 2 ns 6 ns 50 pF 1 k open tPZH, tPHZ [2] VCC < 2 ns 6 ns 50 pF 1 k VEE tPZL, tPLZ [2] VEE < 2 ns 6 ns 50 pF 1 k VCC [1] [2] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor. VI values: a) For 74HC4052: VI = VCC b) For 74HCT4052: VI = 3 V 12. Additional dynamic characteristics Table 12. Additional dynamic characteristics Recommended conditions and typical values; GND = 0 V; Tamb = 25 C; CL = 50 pF. Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output. Symbol Parameter Conditions dsin sine-wave distortion fi = 1 kHz; RL = 10 k; see Figure 16 Min Typ Max Unit Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = 2.25 V - 0.04 - % Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = 4.5 V - 0.02 - % Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = 2.25 V - 0.12 - % Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = 4.5 V - 0.06 - % fi = 10 kHz; RL = 10 k; see Figure 16 iso isolation (OFF-state) Xtalk crosstalk crosstalk voltage Vct f(3dB) 3 dB frequency response RL = 600 ; fi = 1 MHz; see Figure 17 VCC = 2.25 V; VEE = 2.25 V [1] - 50 - dB VCC = 4.5 V; VEE = 4.5 V [1] - 50 - dB VCC = 2.25 V; VEE = 2.25 V [1] - 60 - dB VCC = 4.5 V; VEE = 4.5 V [1] - 60 - dB VCC = 4.5 V; VEE = 0 V - 110 - mV VCC = 4.5 V; VEE = 4.5 V - 220 - mV between two switches/multiplexers; RL = 600 ; fi = 1 MHz; see Figure 18 peak-to-peak value; between control and any switch; RL = 600 ; fi = 1 MHz; E or Sn square wave between VCC and GND; tr = tf = 6 ns; see Figure 19 RL = 50 ; see Figure 20 VCC = 2.25 V; VEE = 2.25 V [2] - 170 - MHz VCC = 4.5 V; VEE = 4.5 V [2] - 180 - MHz [1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ). [2] Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 ). 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 17 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer VCC Sn 10 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah829 Fig 16. Test circuit for measuring sine-wave distortion VCC Sn 0.1 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah871 VCC = 4.5 V; GND = 0 V; VEE = 4.5 V; RL = 600 ; RS = 1 k. a. Test circuit 001aae332 0 αiso (dB) −20 −40 −60 −80 −100 10 102 103 104 105 106 fi (kHz) b. Isolation (OFF-state) as a function of frequency Fig 17. Test circuit for measuring isolation (OFF-state) 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 18 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer VCC Sn 0.1 μF Vis RL nYn/nZ nZ/nYn VEE GND RL CL VCC Sn nYn/nZ nZ/nYn VEE RL GND RL Vos CL dB 001aah873 Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers 2RL 2RL VCC Sn, E Vct nYn G 2RL nZ VEE GND 2RL oscilloscope 001aah913 Fig 19. Test circuit for measuring crosstalk between control input and any switch 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 19 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer VCC Sn 10 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah829 VCC = 4.5 V; GND = 0 V; VEE = 4.5 V; RL = 50 ; RS = 1 k. a. Test circuit 001aad551 5 Vos (dB) 3 1 −1 −3 −5 10 102 103 104 105 106 f (kHz) b. Typical frequency response Fig 20. Test circuit for frequency response 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 20 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 21. Package outline SOT109-1 (SO16) 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 21 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 22. Package outline SOT338-1 (SSOP16) 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 22 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 23. Package outline SOT38-4 (DIP16) 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 23 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 24. Package outline SOT403-1 (TSSOP16) 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 24 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 25. Package outline SOT763-1 (DHVQFN16) 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 25 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 14. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4052 v.10 20120719 Product data sheet - 74HC_HCT4052 v.9 - 74HC_HCT4052 v.8 Modifications: 74HC_HCT4052 v.9 Modifications: • CDM added to features. 20111213 • Product data sheet Legal pages updated. 74HC_HCT4052 v.8 20110511 Product data sheet - 74HC_HCT4052 v.7 74HC_HCT4052 v.7 20110112 Product data sheet - 74HC_HCT4052 v.6 74HC_HCT4052 v.6 20100111 Product data sheet - 74HC_HCT4052 v.5 74HC_HCT4052 v.5 20080505 Product data sheet - 74HC_HCT4052 v.4 74HC_HCT4052 v.4 20041111 Product specification - 74HC_HCT4052 v.3 74HC_HCT4052 v.3 20030516 Product specification - 74HC_HCT4052_CNV v.2 - - - 74HC_HCT4052_CNV v.2 19901201 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 26 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT4052 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 27 of 29 74HC4052; 74HCT4052 NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT4052 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 19 July 2012 © NXP B.V. 2012. All rights reserved. 28 of 29 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Additional dynamic characteristics . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contact information. . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 July 2012 Document identifier: 74HC_HCT4052