74HC590

74HC590 8-bit binary counter with output register; 3-state Rev. 02 — 28 April 2009 Product data sheet 1. General description The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of the register. 2. Features I I I I I Counter and register have independent clock inputs Counter has master reset Complies with JEDEC standard no. 7A Multiple package options ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 2000 V I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Temperature range Name 74HC590N 74HC590D 74HC590PW 74HC590BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C DIP16 SO16 TSSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT38-4 SOT403-1 SOT763-1 Type number Package plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 4. Functional diagram 12 CE 11 CPC 10 MRC 8-BIT BINARY COUNTER 13 CPR 8-BIT STORAGE REGISTER RCO 9 Q0 15 Q1 1 Q2 2 Q3 3 14 OE 3-STATE OUTPUTS Q4 4 Q5 5 Q6 6 Q7 7 001aac542 Fig 1. Functional diagram OE CPR 14 13 12 11 10 EN3 C2 G1 11 CPC 13 CPR RCO Q0 Q1 Q2 9 15 1 CE CPC MRC CTR8 (CT=255)Z4 9 RCO 1+ CT=0 1D 2D 3 15 1 2 3 4 5 6 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 3 4 5 6 7 12 CE Q3 Q4 Q5 Q6 Q7 MRC 10 OE 2D 3 7 14 001aac544 001aac545 Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 2 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state OE 14 CPR 13 CE CPC 12 11 9 RCO T MRC 10 R 1R C1 1S 15 Q0 T R 1R C1 1S 1 Q1 T R 1R C1 1S 2 Q2 T R 1R C1 1S 3 Q3 T R 1R C1 1S 4 Q4 T R 1R C1 1S 5 Q5 T R 1R C1 1S 6 Q6 T R 1R C1 1S 7 Q7 001aac543 Fig 4. Logic diagram 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 3 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 5. Pinning information 5.1 Pinning 74HC590 terminal 1 index area Q2 2 3 4 5 6 7 8 GND RCO 001aac547 16 VCC 15 Q0 14 OE 13 CPR 12 CE 11 CPC 10 MRC 9 74HC590 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 1 2 3 4 5 6 7 8 001aaj535 Q3 Q4 16 VCC 15 Q0 14 OE 13 CPR 12 CE 11 CPC 10 MRC 9 RCO 1 2 3 4 5 6 7 8 001aac564 Q5 74HC590 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 16 VCC 15 Q0 14 OE 13 CPR 12 CE 11 CPC 10 MRC 9 RCO Q6 Q7 GND(1) Transparent top view (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration DIP16 Fig 6. Pin configuration SO16 and TSSOP16 Fig 7. Pin configuration DHVQFN16 5.2 Pin description Table 2. Symbol Q0 to Q7 GND RCO MRC CPC CE CPR OE VCC Pin description Pin 15, 1, 2, 3, 4, 5, 6, 7 8 9 10 11 12 13 14 16 Description parallel data output ground (0 V) ripple carry output (active LOW) master reset counter input (active LOW) counter clock input (active HIGH) count enable input (active LOW) register clock input (active HIGH) output enable input (active LOW) supply voltage 74HC590_2 Product data sheet Rev. 02 — 28 April 2009 1 Q1 © NXP B.V. 2009. All rights reserved. 4 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 6. Functional description Table 3. Inputs OE H L X X X X X X [1] Function table[1] [2] Description CPR X X ↑ ↓ X X X X MRC X X X X L H H H CE X X X X X L L H CPC X X X X X ↑ ↓ X Q outputs disable Q outputs enable counter data stored into register register stage is not changed counter clear advance one count no count no count H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition. RCO = Q0’ · Q1’ · Q2’ · Q3’ · Q4’ · Q5’ · Q6’ · Q7’ (Q0’ to Q7’ are internal outputs of the counter). [2] 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 5 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state CPC CPR MRC CE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 RCO count inhibit counter clear high-impedance OFF-state 001aac548 Fig 8. Typical timing sequence 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 6 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO Parameter supply voltage input clamping current output clamping current output current VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to VCC + 0.5 V RCO standard output Qn bus driver output ICC IGND Tstg Ptot supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C DIP16 package SO16 package TSSOP16 package [1] [2] [2] [1] [1] Conditions Min −0.5 −70 −65 - Max +7.0 ±20 ±20 ±25 ±35 70 +150 750 500 500 Unit V mA mA mA mA mA mA °C mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 packages: Ptot derates linearly with 8 mW/K above 70 °C. For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN16 packages: Ptot derates linearly with 8 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Symbol VCC VI VO ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Tamb ambient temperature Conditions Min 2.0 0 0 −40 Typ 5.0 1.67 Max 6.0 VCC VCC 625 139 83 +125 Unit V V V ns/V ns/V ns/V °C 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 7 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions Min VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level VI = VIH or VIL output voltage all outputs IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V RCO standard output IO = −4 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V Qn bus driver output IO = −6.0 mA; VCC = 4.5 V IO = −7.8 mA; VCC = 6.0 V VOL LOW-level VI = VIH or VIL output voltage all outputs IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V RCO standard output IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V Qn bus driver output IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V II IOZ input leakage current OFF-state output current VI = VCC or GND; VCC = 6.0 V per pin; VI = VIH or VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 6.0 V 0.17 0.18 0.26 0.26 ±0.1 ±0.5 0.33 0.33 ±1.0 ±5.0 0.4 0.4 ±1.0 ±10 V V µA µA 0.17 0.18 0.26 0.26 0.33 0.33 0.4 0.4 V V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V 4.18 4.31 5.68 5.80 4.13 5.63 4.1 5.6 V V 4.18 4.31 5.68 5.80 4.13 5.63 4.1 5.6 V V 1.9 4.4 5.9 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 V V V 1.5 3.15 4.2 25 °C Typ 1.2 2.4 3.2 0.8 2.1 2.8 Max 0.5 1.35 1.8 −40 °C to +85 °C −40 °C to +125 °C Unit Min 1.5 3.15 4.2 Max 0.5 1.35 1.8 Min 1.5 3.15 4.2 Max 0.5 1.35 1.8 V V V V V V ICC CI supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V input capacitance - 3.5 4.0 - - 40 - - 80 - µA pF 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 8 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter tpd propagation delay Conditions CPC to RCO; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPR to Qn; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPLH LOW to HIGH MRC to RCO; see Figure 11 propagation VCC = 2.0 V delay VCC = 4.5 V VCC = 6.0 V ten enable time OE to Qn; see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tdis disable time OE to Qn; see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width CPC and CPR; HIGH or LOW; see Figure 9 and Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MRC; LOW; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time CPC to CPR; see Figure 14 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CE to CPC; see Figure 13 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 74HC590_2 25 °C Min Typ Max [1] −40 °C to +85 °C −40 °C to +125 °C Unit Min Max 190 38 33 175 35 30 165 33 28 130 26 22 130 26 22 Min Max 230 45 40 210 42 36 200 40 34 160 32 27 160 32 27 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns [2] 52 19 15 50 17 14 53 18 14 28 13 11 28 13 11 150 30 26 140 28 24 130 26 22 105 21 18 105 21 18 [3] - 100 20 17 75 15 13 100 20 17 100 20 17 24 9 8 28 8 6 46 14 10 44 11 9 - 125 25 21 95 19 16 125 25 21 125 25 21 - 145 29 25 110 22 19 150 30 26 150 30 26 - ns ns ns ns ns ns ns ns ns ns ns ns 9 of 21 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter th hold time Conditions CE to CPC; see Figure 13 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trec recovery time MRC to CPC; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum frequency CPC or CPR; see Figure 9 and Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance VI = GND to VCC [4] 25 °C Min Typ Max 0 0 0 75 15 13 28 7 6 - −40 °C to +85 °C −40 °C to +125 °C Unit Min 0 0 0 95 19 16 Max Min 0 0 0 110 22 19 Max ns ns ns ns ns ns 6.6 33 39 - 16 52 61 44 - 5.2 26 31 - - 4.4 22 26 - - MHz MHz MHz pF [1] [2] [3] [4] tpd is the same as tPHL, tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 10 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 11. Waveforms 1/fmax VI CPC input GND tW tPHL VOH RCO output VOL VM 001aac550 VM tPLH Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 9. Waveforms showing the propagation delays from the counter clock input (CPC) to ripple carry (RCO) output and the CPC pulse width Measurement points Input VI VM 0.5VCC VCC Output VM 0.5VCC Table 8. Type 74HC590 1/fmax VI CPR input GND tW tPLH VOH Qn output VOL VM 001aac549 VM tPHL Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 10. Waveforms showing the propagation delays from the register clock input (CPR) to output (Qn) and the register clock pulse width 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 11 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state tW VI MRC input GND tPLH VOH RCO output VOL trec VI CPC input GND VM 001aac551 VM VM Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 11. Waveforms showing the propagation delays from the master reset counter input (MRC) to output (RCO), the MRC pulse width and recovery time VI OE input GND output VCC tPLZ tPZL VM 10 % tPHZ output HIGH-to-OFF OFF-to-HIGH VOH 90 % VM GND outputs enabled outputs disabled outputs enabled 001aac554 VM LOW-to-OFF OFF-to-LOW VOL tPZH Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 12. Waveforms showing the 3-state enable and disable times 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 12 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state VI CE input GND tsu VOH CPC input VOL VM 001aac553 VM th tsu th Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 13. Waveforms showing the set-up and hold times for the count enable input (CE) to the counter clock input (CPC) VI CPC input GND tsu VOH CPR input VOL VM 001aac552 VM th Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 14. Waveforms showing the set-up and hold times for the counter clock input (CPC) to the register clock input (CPR) 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 13 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 15. Test circuit for measuring switching times Table 9. VCC 2.0 V to 6.0 V Test data Input VI VCC tr, tf 6 ns Load CL 50 pF RL 1 kΩ Switch position tPHL, tPLH open tPZH, tPHZ GND tPZL, tPLZ VCC Supply voltage 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 14 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 16. Package outline SOT38-4 (DIP16) 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 15 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 17. Package outline SOT109-1 (SO16) 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 16 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 18. Package outline SOT403-1 (TSSOP16) 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 17 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 19. Package outline SOT763-1 (DHVQFN16) 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 18 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 13. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20090428 Data sheet status Product data sheet Change notice Supersedes 74HC590_1 Document ID 74HC590_2 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Quick reference data incorporated in to Section 9 and Section 10. Added type number 74HC590N (DIP16 package) Product data sheet - 74HC590_1 20050330 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 19 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC590_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 20 of 21 NXP Semiconductors 74HC590 8-bit binary counter with output register; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 April 2009 Document identifier: 74HC590_2