74HC597D/AUJ

74HC597; 74HCT597 8-bit shift register with input flip-flops Rev. 5 — 26 October 2021 Product data sheet 1. General description The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Input levels: • For 74HC597: CMOS level • For 74HCT597: TTL level 8-bit parallel storage register inputs Shift register has direct overriding load and clear Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) ESD protection: • HBM EIA/JESD22-A114F exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT597DB -40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC597PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HC597D 74HCT597D 74HCT597PW 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 4. Functional diagram STCP 12 D0 D1 D2 D3 D4 D5 D6 D7 MR 10 DS 14 STCP MR DS 12 10 14 15 1 D0 15 2 D1 1 D2 2 D3 3 5 D4 4 6 D5 5 D6 6 D7 7 3 4 INPUT FLIP-FLOPS 8-BIT SHIFT REGISTER 7 9 13 PL Q INPUT FLIPFLOPS 11 SHCP aaa-012057 Fig. 1. Functional diagram Fig. 2. R 10 11 9 13 11 PL SHCP Q aaa-012056 Logic symbol SRG8 C3/ C2 13 12 8-BIT SHIFT REGISTER C1 1 14 3D 15 1D 2D 1 1D 2D 2 3 4 5 6 9 7 aaa-012055 Fig. 3. IEC Logic symbol 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 2 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops MR SHCP PL STCP DS D0 C2 S 2D 1D C1 D1 R C3 3S S 3R 1D C1 D2 R C3 3S S 3R 1D C1 D3 R C3 3S S 3R 1D C1 D4 R C3 3S S 3R 1D C1 D5 R C3 3S S 3R 1D C1 D6 R C3 3S S 3R 1D C1 D7 R C3 3S S 3R 1D Q C1 R aaa-012058 Fig. 4. Logic diagram 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 3 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 5. Pinning information 5.1. Pinning 74HC597 74HCT597 D1 1 16 VCC D2 2 15 D0 D3 3 14 DS D4 4 13 PL D5 5 74HC597 74HCT597 D1 1 D2 2 16 VCC 15 D0 D3 3 14 DS D4 4 13 PL 12 STCP D5 5 12 STCP D6 6 11 SHCP D7 7 10 MR GND 8 D6 6 11 SHCP D7 7 10 MR GND 8 9 Q Q aaa-012054 aaa-012939 Fig. 5. 9 Fig. 6. Pin configuration SOT109-1 (SO16) Pin configuration SOT338-1 (SSOP16) and SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description GND 8 ground (0 V) Q 9 serial data output MR 10 asynchronous master reset input (active LOW) SHCP 11 shift register clock input (LOW-to-HIGH, edge-triggered) STCP 12 storage register clock input (LOW-to-HIGH, edge-triggered) PL 13 parallel load input (active LOW) DS 14 serial data input D0, D1, D2, D3, D4, D5, D6, D7 15, 1, 2, 3, 4, 5, 6, 7 parallel data inputs VCC 16 supply voltage 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 4 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition. Inputs Function STCP SHCP PL MR ↑ X X X data loaded to input latches ↑ X L H data loaded from inputs to shift register no clock edge X L H data transferred from input flip-flops to shift register X X L L invalid logic, state of shift register is indeterminate when signals removed X X H L shift register cleared X ↑ H H shift register clocked Qn = Qn-1, Q0 = DS SHCP DS MR PL STCP D0 H L L D1 L L L D2 H L L D3 L L L D4 H L H D5 H L H D6 L L L D7 H H L L Q reset shift register H L H H L H L H L H serial shift L L L L L serial shift H H serial shift serial shift load input register Fig. 7. L parallel load shift register load input register parallel load shift register parallel load both input and shift registers aaa-012059 Timing diagram 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 5 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +7 V VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA ICC supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT338-1 (SSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC597 74HCT597 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 6 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 VCC = 4.5 V 3.15 2.4 - 1.5 - 3.15 - 1.5 - V - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V LOW-level input VCC = 2.0 V voltage VCC = 4.5 V - 0.8 0.5 - 0.5 - 0.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V 74HC597 VIH VIL VOH VOL HIGH-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80.0 - 160.0 μA CI input capacitance - 3.5 - - - - - pF 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 7 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 2.0 1.6 - 2.0 - 2.0 - V - 1.2 0.8 - 0.8 - 0.8 V IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 μA - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA 74HCT597 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V VIL LOW-level input VCC = 4.5 V to 5.5 V voltage VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80.0 - 160.0 μA ΔICC additional supply current VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; DS input - 25 90 - 112.5 - 122.5 μA per input pin; Dn inputs - 30 108 - 135 - 147 μA per input pin; PL, MR inputs - 150 540 - 675 - 735 μA per input pin; STCP, SHCP inputs - 150 540 - 675 - 735 μA - 3.5 - - - - - pF VOL CI input capacitance 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 8 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 14. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 55 175 - 220 - 265 ns VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 30 - 37 - 45 ns VCC = 2.0 V - 58 175 - 220 - 265 ns VCC = 4.5 V - 21 35 - 44 - 53 ns VCC = 6.0 V - 17 30 - 37 - 45 ns VCC = 2.0 V - 80 250 - 315 - 375 ns VCC = 4.5 V - 29 50 - 63 - 75 ns VCC = 5.0 V; CL = 15 pF - 25 - - - - - ns VCC = 6.0 V - 23 43 - 54 - 64 ns VCC = 2.0 V - 69 215 - 270 - 325 ns VCC = 4.5 V - 25 43 - 54 - 65 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns VCC = 6.0 V - 20 37 - 46 - 55 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns 74HC597 tpd propagation SHCP to Q; see Fig. 8 delay VCC = 2.0 V [1] MR to Q; see Fig. 9 [1] STCP to Q; see Fig. 8 [1] PL to Q; see Fig. 10 tt transition time 74HC_HCT597 Product data sheet Q; see Fig. 10 [1] [2] All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 9 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops Symbol Parameter tW pulse width Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 80 11 - 100 - 120 - ns VCC = 4.5 V 16 4 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 60 -3 - 75 - 90 - ns VCC = 4.5 V 12 -1 - 15 - 18 - ns VCC = 6.0 V 10 -1 - 13 - 15 - ns VCC = 2.0 V 60 8 - 75 - 90 - ns VCC = 4.5 V 12 3 - 15 - 18 - ns VCC = 6.0 V 10 2 - 13 - 15 - ns VCC = 2.0 V 60 11 - 75 - 90 - ns VCC = 4.5 V 12 4 - 15 - 18 - ns VCC = 6.0 V 10 3 - 13 - 15 - ns VCC = 2.0 V 60 11 - 75 - 90 - ns VCC = 4.5 V 12 4 - 15 - 18 - ns VCC = 6.0 V 10 3 - 13 - 15 - ns VCC = 2.0 V 5 -3 - 5 - 5 - ns VCC = 4.5 V 5 -1 - 5 - 5 - ns VCC = 6.0 V 5 -1 - 5 - 5 - ns VCC = 2.0 V 5 -6 - 5 - 5 - ns VCC = 4.5 V 5 -2 - 5 - 5 - ns VCC = 6.0 V 5 -2 - 5 - 5 - ns STCP HIGH or LOW; see Fig. 8 SHCP HIGH or LOW; see Fig. 8 MR LOW; see Fig. 9 PL LOW; see Fig. 10 trec tsu recovery time set-up time MR to SHCP; see Fig. 11 Dn to STCP; see Fig. 12 DS to SHCP; see Fig. 12 PL to SHCP; see Fig. 13 th hold time Dn to STCP; see Fig. 12 PL, DS to SHCP; see Fig. 12 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 10 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops Symbol Parameter fmax maximum frequency Conditions 25 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 6.0 29 - 4.8 - 4.0 - MHz VCC = 4.5 V 30 87 - 24 - 20 - MHz - 96 - - - - - MHz 35 104 - 28 - 24 - MHz - 29 - - - - - pF - 23 40 - 50 - 60 ns - 20 - - - - - ns - 28 49 - 61 - 74 ns VCC = 4.5 V - 33 57 - 71 - 86 ns VCC = 5.0 V; CL = 15 pF - 29 - - - - - ns VCC = 4.5 V - 30 52 - 65 - 78 ns VCC = 5.0 V; CL = 15 pF - 26 - - - - - ns - 7 15 - 19 - 22 ns 16 6 - 20 - 24 - ns 16 7 - 20 - 24 - ns 25 14 - 31 - 38 - ns 20 10 - 25 - 30 - ns 12 -2 - 15 - 18 - ns 12 5 - 15 - 18 - ns 12 2 - 15 - 18 - ns 12 4 - 15 - 18 - ns 5 -1 - 5 - 5 - ns 5 -2 - 5 - 5 - ns SHCP; see Fig. 8 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD -40 °C to +85 °C power CL = 50 pF; f = 1 MHz; dissipation VI = GND to VCC capacitance [3] 74HCT597 tpd propagation SHCP to Q; see Fig. 8 delay VCC = 4.5 V [1] VCC = 5.0 V; CL = 15 pF MR to Q; see Fig. 9 [1] VCC = 4.5 V STCP to Q; see Fig. 8 [1] PL to Q; see Fig. 10 tt tW transition time Q; see Fig. 10 pulse width STCP HIGH or LOW; see Fig. 8 [1] [2] VCC = 4.5 V VCC = 4.5 V SHCP HIGH or LOW; see Fig. 8 VCC = 4.5 V MR LOW; see Fig. 9 VCC = 4.5 V PL LOW; see Fig. 10 VCC = 4.5 V trec tsu recovery time MR to SHCP; see Fig. 11 set-up time Dn to STCP; see Fig. 12 VCC = 4.5 V VCC = 4.5 V DS to SHCP; see Fig. 12 VCC = 4.5 V PL to SHCP; see Fig. 13 VCC = 4.5 V th hold time Dn to STCP; see Fig. 12 VCC = 4.5 V PL, DS to SHCP; see Fig. 12 VCC = 4.5 V 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 11 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops Symbol Parameter fmax maximum frequency Conditions 25 °C [1] [2] [3] -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 30 75 - 24 - 20 - MHz - 83 - - - - - MHz - 32 - - - - - pF SHCP; see Fig. 8 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CPD -40 °C to +85 °C power CL = 50 pF; f = 1 MHz; dissipation VI = GND to VCC - 1.5 V capacitance [3] tpd is the same as tPLH and tPHL. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 10.1. Waveforms and test circuit 1/fmax VI STCP, SHCP input VM GND VOH tW tPHL tPLH Q output VM VOL aaa-012368 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. SHCP and STCP clock inputs to Q output propagation delays, pulse width and maximum clock frequency VI VM MR input GND VOH Q output tW tPHL VM VOL aaa-012369 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Input MR to Q output propagation delays and MR pulse width 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 12 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 1/fmax VI VM PL input GND tW tPLH tPHL VOH 90 % Q output VOL 90 % VM 10 % 10 % tTHL tTLH aaa-012371 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 10. Input PL to Q output propagation delays, PL pulse width and output transition times VI VM MR input GND trec VI SHCP input VM GND aaa-012372 Measurement points are given in Table 8. Fig. 11. Input MR to shift clock SHCP and storage clock STCP recovery times positive DS, Dn input VI VM GND negative DS, Dn input VI VM GND tsu th VI VM SHCP input GND VI VM STCP input GND tsu th aaa-012374 Measurement points are given in Table 8. Fig. 12. Set-up and hold times for DS, Dn inputs to SHCP, STCP inputs 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 13 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops VI PL input VM GND VI VM SHCP input GND tsu th aaa-012375 Measurement points are given in Table 8. Fig. 13. Set-up and hold times for PL input to SHCP input Table 8. Measurement points Type Input Output VM VI VM 74HC597 0.5 × VCC GND to VCC 0.5 × VCC 74HCT597 1.3 V GND to 3 V 1.3 V VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VCC VO RT RL S1 open CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig. 14. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC597 VCC 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HCT597 3V 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 14 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 15. Package outline SOT109-1 (SO16) 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 15 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig. 16. Package outline SOT338-1 (SSOP16) 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 16 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 17. Package outline SOT403-1 (TSSOP16) 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 17 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT597 v.5 20211026 Product data sheet - Modifications: • • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74HC597DB (SOT338-1/SSOP16) removed. Type number 74HCT597PW (SOT403-1/TSSOP16) added. Section 2 updated. Table 4: Derating values for Ptot total power dissipation updated. 74HC_HCT597 v.4 20160225 Modifications: • 74HC_HCT597 v.3 20140415 Modifications: • • 74HC_HCT597_CNV v.2 74HC_HCT597 Product data sheet 74HC_HCT597 v.4 Product data sheet - 74HC_HCT597 v.3 Type numbers 74HC597N and 74HCT597N (SOT38-4) removed. Product data sheet - 74HC_HCT597_CNV v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 19901201 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 - © Nexperia B.V. 2021. All rights reserved 18 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC_HCT597 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 19 / 20 74HC597; 74HCT597 Nexperia 8-bit shift register with input flip-flops Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 4 6. Functional description................................................. 5 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................6 9. Static characteristics....................................................7 10. Dynamic characteristics............................................ 9 10.1. Waveforms and test circuit...................................... 12 11. Package outline........................................................ 15 12. Abbreviations............................................................ 18 13. Revision history........................................................18 14. Legal information......................................................19 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 26 October 2021 74HC_HCT597 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 20 / 20