74HC75D,653

74HC75 Quad bistable transparant latch Rev. 5 — 17 March 2021 Product data sheet 1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) Complementary Q and Q outputs VCC and GND on the center pins CMOS input levels ESD protection: • HBM EIA/JESD22-A114F exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V Specified from -40 °C to +80 °C and from -40 °C to +125 °C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC75D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC75PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HC75 Nexperia Quad bistable transparant latch 4. Functional diagram 13 13 3 1Q 1D 1Q 2Q 2D L1,2 L3,4 6 7 3D 3Q 4Q 4Q LE34 4 Fig. 1. 2Q 3Q 4D 16 13 1D LE12 14 2D Q 8 4 LE34 4D 1Q 2Q 3Q 3Q CP IEC logic symbol 16 1 1D D 4Q 4Q 14 2D D 74HC75 Product data sheet 1Q Q 2Q 2Q LATCH 2 10 11 3D D Q 3Q CP 3Q LATCH 3 9 8 4D D Q 4Q CP 4Q LATCH 4 001aab853 Functional diagram 1Q LATCH 1 L4 Fig. 3. Q CP 15 LE34 Q CP 11 CP Q D 10 001aab852 L3 7 8 6 2Q D 1D 9 L2 3D 9 7 11 LE12 CP 6 C1 10 1Q CP D 14 4 L1 3 15 001aab851 Q 1 15 Fig. 2. D 1D 3 1 Logic symbol 2 16 2 LE12 2 C1 Fig. 4. 001aab854 Logic diagram All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 2 / 16 74HC75 Nexperia Quad bistable transparant latch 5. Pinning information 5.1. Pinning 74HC75 1Q 1 16 1Q 1D 2 15 2Q 2D 3 14 2Q LE34 4 13 LE12 VCC 5 12 GND 3D 6 11 3Q 4D 7 4Q 8 74HC75 1Q 1 16 1Q 1D 2 15 2Q 2D 3 14 2Q LE34 4 13 LE12 VCC 5 12 GND 3D 6 11 3Q 4D 7 10 3Q 4Q 8 10 3Q 9 4Q 001aab850 Fig. 5. 9 4Q aaa-033311 Pin configuration SOT109-1 (SO16) Fig. 6. Pin configuration SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1Q, 2Q, 3Q, 4Q 1, 14, 11, 8 complementary latch output 1D, 2D, 3D, 4D 2, 3, 6, 7 data input LE34 4 latch enable input for latches 3 and 4 (active HIGH) VCC 5 positive supply voltage GND 12 ground (0 V) LE12 13 latch enable input for latches 1 and 2 (active HIGH) 1Q, 2Q, 3Q, 4Q 16, 15, 10, 9 latch output 6. Function description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW LEnn transition. Operating mode Data enabled Data latched 74HC75 Product data sheet Input Output LEnn nD nQ nQ H L L H H H H L L X q q All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 3 / 16 74HC75 Nexperia Quad bistable transparant latch 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC supply voltage -0.5 +7.0 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V IO output current VO = -0.5 V to VCC + 0.5 V [1] - ±20 mA - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Conditions Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature -40 - +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V Tamb = 25 °C VIH VIL HIGH-level input voltage LOW-level input voltage 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 4 / 16 74HC75 Nexperia Quad bistable transparant latch Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL VOL LOW-level output voltage Min Typ Max Unit IO = -20 μA; VCC = 2.0 V 1.9 2.0 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - V IO = -4 mA; VCC = 4.5 V 3.98 4.32 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 μA CI input capacitance - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 - - V IO = -20 μA; VCC = 4.5 V 4.4 - - V IO = -20 μA; VCC = 6.0 V 5.9 - - V IO = -4 mA; VCC = 4.5 V 3.84 - - V IO = -5.2 mA; VCC = 6.0 V 5.34 - - V IO = 20 μA; VCC = 2.0 V - - 0.1 V IO = 20 μA; VCC = 4.5 V - - 0.1 V IO = 20 μA; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V Tamb = -40 °C to +85 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 μA 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 5 / 16 74HC75 Nexperia Quad bistable transparant latch Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V Tamb = -40 °C to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL - IO = -20 μA; VCC = 2.0 V 1.9 - - V IO = -20 μA; VCC = 4.5 V 4.4 - - V IO = -20 μA; VCC = 6.0 V 5.9 - - V IO = -4 mA; VCC = 4.5 V 3.7 - - V IO = -5.2 mA; VCC = 6.0 V 5.2 - - V VI = VIH or VIL - IO = 20 μA; VCC = 2.0 V - - 0.1 V IO = 20 μA; VCC = 4.5 V - - 0.1 V IO = 20 μA; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 μA 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 6 / 16 74HC75 Nexperia Quad bistable transparant latch 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specified, for test circuit see Fig. 11. Symbol Parameter Min Typ Max Unit VCC = 2.0 V - 33 110 ns VCC = 4.5 V - 12 22 ns VCC = 6.0 V - 10 19 ns VCC = 5.0 V; CL = 15 pF - 11 - ns VCC = 2.0 V - 39 120 ns VCC = 4.5 V - 14 24 ns VCC = 6.0 V - 11 20 ns VCC = 5.0 V; CL = 15 pF - 11 - ns VCC = 2.0 V - 33 120 ns VCC = 4.5 V - 12 24 ns VCC = 6.0 V - 10 20 ns VCC = 5.0 V; CL = 15 pF - 11 - ns VCC = 2.0 V - 39 125 ns VCC = 4.5 V - 14 25 ns VCC = 6.0 V - 11 21 ns VCC = 5.0 V; CL = 15 pF - 11 - ns VCC = 2.0 V - 19 75 ns VCC = 4.5 V - 7 15 ns VCC = 6.0 V - 6 13 ns VCC = 2.0 V 80 17 - ns VCC = 4.5 V 16 6 - ns VCC = 6.0 V 14 5 - ns VCC = 2.0 V 60 14 - ns VCC = 4.5 V 12 5 - ns VCC = 6.0 V 10 4 - ns VCC = 2.0 V 3 -8 - ns VCC = 4.5 V 3 -3 - ns VCC = 6.0 V 3 -2 - ns - 42 - pF Conditions Tamb = 25 °C tpd propagation delay nD to nQ; see Fig. 7 nD to nQ; see Fig. 8 LEnn to nQ; see Fig. 10 LEnn to nQ; see Fig. 10 tt tW tsu th CPD transition time pulse width set-up time hold time power dissipation capacitance 74HC75 Product data sheet nQ, nQ; see Fig. 7 and Fig. 8 [1] [1] [1] [1] [2] LEnn HIGH; see Fig. 10 nD to LEnn; see Fig. 9 nD to LEnn; see Fig. 9 per latch; VI = GND to VCC [3] All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 7 / 16 74HC75 Nexperia Quad bistable transparant latch Symbol Parameter Min Typ Max Unit VCC = 2.0 V - - 140 ns VCC = 4.5 V - - 28 ns VCC = 6.0 V - - 24 ns VCC = 2.0 V - - 150 ns VCC = 4.5 V - - 30 ns VCC = 6.0 V - - 26 ns VCC = 2.0 V - - 150 ns VCC = 4.5 V - - 30 ns - - 26 ns VCC = 2.0 V - - 155 ns VCC = 4.5 V - - 31 ns VCC = 6.0 V - - 26 ns VCC = 2.0 V - - 95 ns VCC = 4.5 V - - 19 ns VCC = 6.0 V - - 16 ns VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns VCC = 2.0 V 75 - - ns VCC = 4.5 V 15 - - ns VCC = 6.0 V 13 - - ns VCC = 2.0 V 3 - - ns VCC = 4.5 V 3 - - ns VCC = 6.0 V 3 - - ns Conditions Tamb = -40 °C to +85 °C tpd propagation delay nD to nQ; see Fig. 7 nD to nQ; see Fig. 8 LEnn to nQ; see Fig. 10 [1] [1] [1] VCC = 6.0 V LEnn to nQ; see Fig. 10 tt tW tsu th transition time pulse width set-up time hold time 74HC75 Product data sheet nQ, nQ; see Fig. 7 and Fig. 8 [1] [2] LEnn HIGH; see Fig. 10 nD to LEnn; see Fig. 9 nD to LEnn; see Fig. 9 All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 8 / 16 74HC75 Nexperia Quad bistable transparant latch Symbol Parameter Min Typ Max Unit VCC = 2.0 V - - 165 ns VCC = 4.5 V - - 33 ns VCC = 6.0 V - - 28 ns VCC = 2.0 V - - 180 ns VCC = 4.5 V - - 36 ns VCC = 6.0 V - - 31 ns VCC = 2.0 V - - 180 ns VCC = 4.5 V - - 36 ns - - 31 ns VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 32 ns VCC = 2.0 V - - 110 ns VCC = 4.5 V - - 22 ns VCC = 6.0 V - - 19 ns VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns VCC = 2.0 V 90 - - ns VCC = 4.5 V 18 - - ns VCC = 6.0 V 15 - - ns VCC = 2.0 V 3 - - ns VCC = 4.5 V 3 - - ns VCC = 6.0 V 3 - - ns Conditions Tamb = -40 °C to +125 °C tpd propagation delay nD to nQ; see Fig. 7 nD to nQ; see Fig. 8 LEnn to nQ; see Fig. 10 [1] [1] [1] VCC = 6.0 V LEnn to nQ; see Fig. 10 tt transition time tW pulse width tsu set-up time th [1] [2] [3] hold time nQ, nQ; see Fig. 7 and Fig. 8 [1] [2] LEnn HIGH; see Fig. 10 nD to LEnn; see Fig. 9 nD to LEnn; see Fig. 9 tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of outputs. 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 9 / 16 74HC75 Nexperia Quad bistable transparant latch 10.1. Waveforms and test circuit nD input VM tPHL nQ output tPLH VM tTHL tTLH 001aab855 VM = 0.5 × VI Fig. 7. Waveforms showing the data input (nD) to output (nQ) propagation delays and the output transition times nD input VM tPHL nQ output tPLH VM tTHL tTLH 001aab856 VM = 0.5 × VI Fig. 8. Waveforms showing the data input (nD) to output (nQ) propagation delays and the output transition times nD input VM th tsu VM LEnn input nQ output th tsu Q=D Q=D 001aab858 The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5 × VI Fig. 9. Waveforms showing the data set-up and hold times for nD input to LEnn input 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 10 / 16 74HC75 Nexperia Quad bistable transparant latch nD input LEnn input VM tW tPHL VM nQ output tPLH nQ output tPLH tTHL tPHL tTLH VM tTLH tTHL 001aab857 VM = 0.5 × VI Fig. 10. Waveforms showing the latch enable input (LEnn) pulse width, the latch enable input to outputs (nQ, nQ) propagation delays and the output transition times VCC PULSE GENERATOR VI DUT VO RT CL mna101 Test data is given in Table 8 Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance Fig. 11. Test circuit for measuring switching times Table 8. Test data Supply Input VCC VI tr, tf CL 2.0 V VCC 6 ns 50 pF 4.5 V VCC 6 ns 50 pF 6.0 V VCC 6 ns 50 pF 5.0 V VCC 6 ns 15 pF 74HC75 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 11 / 16 74HC75 Nexperia Quad bistable transparant latch 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 12. Package outline SOT109-1 (SO16) 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 12 / 16 74HC75 Nexperia Quad bistable transparant latch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 13. Package outline SOT403-1 (TSSOP16) 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 13 / 16 74HC75 Nexperia Quad bistable transparant latch 12. Abbreviations Table 9. Abbreviations Acronym Abbreviation CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 13. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC75 v.5 20210317 Product data sheet - 74HC75 v.4 Modifications: • • • 74HC75 v.4 20160224 Modifications: • 74HC75 v.3 20041112 Modifications: • • • Section 2 updated. Section 7: Derating values for Ptot total power dissipation updated. Type number 74HC75DB (SOT338-1 / SSOP16) removed. Product data sheet - 74HC75 v.3 Type number 74HC75N (SOT38-4) removed. Product data sheet - 74HC_HCT75_CNV v.2 The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. Removed type number 74HCT75. Inserted family specification. 74HC_HCT75_CNV v.2 19970918 Product specification - 74HC_HCT75 v.1 74HC_HCT75 v.1 19901201 Product specification - - 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 14 / 16 74HC75 Nexperia Quad bistable transparant latch 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC75 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 15 / 16 74HC75 Nexperia Quad bistable transparant latch Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Function description.................................................... 3 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................4 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 12 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 17 March 2021 74HC75 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 17 March 2021 © Nexperia B.V. 2021. All rights reserved 16 / 16