74HC7731N,112

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7731 Quad 64-bit static shift register Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Quad 64-bit static shift register FEATURES • Frequency range DC to 100 MHz. • Separate serial data inputs • Cascadable 74HC/HCT7731 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYP. SYMBOL PARAMETER CONDITIONS UNIT HC HCT 15 20 • Functionally compatible with HEF 4731 tPHL/tPLH • Includes recycling mode propagation delay CPa-d to Qa-d fmax maximum clock frequency 100 100 MHz • Output capability: Standard CI input capacitance 3.5 3.5 pF • ICC category: LSI. CPD power dissipation capacitance per register 58 61 pF • Direct shift out CL = 15 pF; VCC = 5 V notes 1, 2 and 3 ns APPLICATIONS Notes • Data storage 1. CPD is used to determine the dynamic power dissipation (PD in µW): • Delay line. GENERAL DESCRIPTION The HC/HCT7731 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The HC/HCT7731 are quad 64-bit static shift registers with a recycling mode. Each register has separate data inputs Da to Dd, clock inputs CPa to CPd and data outputs Qa to Qd. Data shifts one place towards the output, each LOW to HIGH transition of the clock pulse. Each recycling mode input controls two registers RECab for registers A and B and RECcd for registers C and D. When the REC input is HIGH, the device is in the recycling mode and data at the output is shifted back into the input of the register, so after 64 clock pulses the contents of a register is again in its original position. This enables the user to tap off data from any position. When the REC input is LOW external data can be shifted in. September 1993 PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) where: fi = input frequency in MHz. fo = output frequency in MHz. VCC = supply voltage in V. CL = output load capacitance in pF. Ipull-up = pull-up currents in µA. 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V. 3. See also power dissipation information. ORDERING INFORMATION EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE 74HC/HCT7731N 16 DIL plastic SOT38Z 74HC/HCT7731D 16 SO16 plastic SOT109A 2 Philips Semiconductors Product specification Quad 64-bit static shift register 74HC/HCT7731 PINNING SYMBOL PIN DESCRIPTION Qa to Qd 1, 7, 9, 15 data outputs CPa to CPd 2, 6, 10, 14 clock inputs Da to Dd 3, 5, 11, 13 data inputs RECab, RECcd 4, 12 handbook, halfpage recycled enable input GND 8 ground (0 V) VCC 16 positive supply Qa 1 16 VCC CP a 2 15 Q d Da 3 14 CP d REC ab 4 13 Dd 7731 Db 5 12 RECcd CP b 6 11 D c Qb 7 10 CP c GND 8 9 Qc MBA341 Fig.1 Pin configuration. handbook, full pagewidth 3 Da MUX 64 - BIT STATIC SHIFT REGISTER Qa MUX 64 - BIT STATIC SHIFT REGISTER Qb 7 MUX 64 - BIT STATIC SHIFT REGISTER Qc MUX 64 - BIT STATIC SHIFT REGISTER Q d 15 2 CP a 1 4 REC ab 5 Db 6 CP b 11 D c 10 CP c 9 12 RECcd 13 D d 14 CP d MBA342 Fig.2 Functional diagram. September 1993 3 Philips Semiconductors Product specification Quad 64-bit static shift register 74HC/HCT7731 handbook, full pagewidth REC n D Q FF1 Dn CP CP n Q FF2 CP D Qn Q FF64 CP MBA345 to second shift register Fig.3 Logic diagram. FUNCTION TABLE INPUT OUTPUT REC CP MODE L ↑ shift H ↑ recycle Notes 1. L = LOW voltage level H = HIGH voltage Level ↑ = LOW-to-HIGH CP transition September 1993 D 4 Philips Semiconductors Product specification Quad 64-bit static shift register 74HC/HCT7731 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: LSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) SYMBOL +25 PARAMETER MIN TYP MAX TEST CONDITION −40 to +85 −40 to +125 MIN MIN MAX UNIT VCC (V) MAX WAVEFORMS tPHL/tPLH propagation delay time CP to Qn − − − 50 18 15 155 31 26 − − − 190 38 32 − − − 230 46 39 ns ns ns 2.0 4.5 6.0 Fig.4 tTHL/tTLH output transition − time − − 19 7 6 75 15 13 − − − 90 18 15 − − − 110 22 19 ns ns ns 2.0 4.5 6.0 Fig.4 tW clock pulse width HIGH or LOW 80 16 14 19 7 6 − − − 100 20 17 − − − 120 24 20 − − − ns ns ns 2.0 4.5 6.0 Fig.4 tsu set-up time Dn to CPn 60 12 10 8 3 3 − − − 75 15 13 − − − 90 18 15 − − − ns ns ns 2.0 4.5 6.0 Fig.4 tsu set-up time RECn to CPn 75 15 13 22 8 7 − − − 90 18 15 − − − 110 22 19 − − − ns ns ns 2.0 4.5 6.0 Fig.5 th hold time Dn to CPn 25 5 4 −3 −1 −1 − − − 30 6 5 − − − 35 7 6 − − − ns ns ns 2.0 4.5 6.0 Fig.4 th hold time RECn to CPn 10 2 2 −8 −3 −3 − − − 10 2 2 − − − 15 3 3 − − − ns ns ns 2.0 4.5 6.0 Fig.5 fmax maximum clock 6 pulse frequency 30 35 26 78 93 − − − 4.8 24 28 − − − 4 20 23 − − − MHz MHZ MHz 2.0 4.5 6.0 Fig.4 (note 1) Note 1. The maximum power dissipation has to be observed. See power dissipation information. September 1993 5 Philips Semiconductors Product specification Quad 64-bit static shift register 74HC/HCT7731 UNIT LOAD COEFFICIENT INPUT UNIT LOAD COEFFICIENT CPn 0.7 RECn 0.4 Dn 0.5 Notes 1. The RS input has CMOS input switching levels. 2. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in Table 1. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) SYMBOL +25 PARAMETER TEST CONDITION −40 to +85 −40 to +125 UNIT MIN TYP MAX MIN MAX MIN MAX VCC (V) WAVEFORMS tPHL/tPLH propagation delay time CP to Qn − 24 42 − 52 − 63 ns 4.5 Fig.4 tTHL/tTLH output transmission time − 7 15 − 18 − 22 ns 4.5 Fig.4 tW clock pulse width HIGH or LOW 16 7 − 20 − 24 − ns 4.5 Fig.4 tsu set-up time Dn to CPn 12 3 − 15 − 18 − ns 4.5 Fig.4 tsu set-up time RECn to CPn 15 6 − 18 − 22 − ns 2 Fig.5 th hold time Dn to CPn 5 0 − 6 − 7 − ns 2 Fig.4 th hold time RECn to CPn 2 −3 − 2 − 3 − ns 4.5 Fig.5 fmax maximum clock pulse frequency 30 80 − 24 − 20 − MHz 4.5 Fig.4 (note 1) September 1993 6 Philips Semiconductors Product specification Quad 64-bit static shift register 74HC/HCT7731 AC WAVEFORMS 1/ f max handbook, full pagewidth CPn INPUT V M (1) tW tsu tsu th th V M (1) Dn INPUT t PLH t PHL V M (1) Q n OUTPUT t TLH MBA320 t THL (1) HC : VM = 50%; VI = GND to VCC HCT : VM = 1.3 V; VI = GND to 3 V. Fig.4 Waveforms showing the clock (CP) and data (D) input to output (Q) propagation delay, set-up, hold and transition times. 1/ f max handbook, full pagewidth CPn INPUT V M (1) tW t su REC n INPUT th t su th V M (1) MBA321 (1) HC : VM = 50%; VI = GND to VCC HCT : VM = 1.3 V; VI = GND to 3 V. Fig.5 Waveforms showing the clock (CP) to recycle (REC) set-up and hold times. September 1993 7 Philips Semiconductors Product specification Quad 64-bit static shift register 74HC/HCT7731 POWER DISSIPATION INFORMATION The power dissipation per register operating at the same frequency is given by: PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) MLA166 60 handbook, halfpage CPD (pF) 40 fi = clock input frequency fo = data output frequency CL = output load capacitance in pF VCC = power supply voltage in V. As PD also depends on the frequency at which the contents of the internal bits are changing, the value of CPD is a function of the duty factor (df) being the ration between data and clock frequency, see Fig.6. 20 Example: 0 0 0.2 0.4 duty factor 0.6 fi = 12 MHz fo = 3 MHz CL = 25 pF VCC =5V df = 3/12 = 0.25 CPD = 42.5 pF PD = (42.5 × 52 × 12) + (25 × 52 × 3) = 14625 µW Fig.6 CPD as a function of the duty factor. As the maximum allowable power dissipation in an SO package at Tamb = 125 °C is 60 mW, it is allowed to apply 4 registers at the same time under these conditions. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. September 1993 8