74HCT3G07DC

74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs Rev. 02 — 12 May 2009 Product data sheet 1. General description The 74HC3G07 and 74HCT3G07 are high-speed Si-gate CMOS devices. They provide three buffers with open-drain outputs. The outputs of the 74HC3G07 and 74HCT3G07 devices are open drains and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. For digital operation this device must have a pull-up resistor to establish a logic HIGH-level. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V. The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features I I I I I Wide supply voltage range from 2.0 V to 6.0 V High noise immunity Low power dissipation Multiple package options ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74HC3G07DP 74HCT3G07DP 74HC3G07DC 74HCT3G07DC 74HC3G07GD 74HCT3G07GD −40 °C to +125 °C XSON8U −40 °C to +125 °C VSSOP8 −40 °C to +125 °C TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs 4. Marking Table 2. Marking code Marking code H07 T07 H07 T07 H07 T07 Type number 74HC3G07DP 74HCT3G07DP 74HC3G07DC 74HCT3G07DC 74HC3G07GD 74HCT3G07GD 5. Functional diagram 1 1A 1Y 1A 1Y 1 2A 2Y 2A 2Y Y 3A 3Y 3A 001aah762 1 3Y 001aah763 A GND mna591 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 6. Pinning information 6.1 Pinning 74HC3G07 74HCT3G07 1A 1 2 3 4 8 7 6 5 VCC 1Y 3A 2Y 74HC3G07 74HCT3G07 1A 3Y 2A GND 1 2 3 4 001aak032 3Y 8 7 6 5 VCC 1Y 3A 2Y 2A GND 001aak033 Transparent top view Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8U) 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 2 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs 6.2 Pin description Table 3. Symbol 1A, 2A, 3A GND 1Y, 2Y, 3Y VCC Pin description Pin 1, 3, 6 4 7, 5, 2 8 Description data input ground (0 V) data output supply voltage 7. Functional description Table 4. Input nA L H [1] Function table[1] Output nY L Z H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK VO IO ICC IGND Tstg PD [1] [2] Parameter supply voltage input clamping current output clamping current output voltage output current supply current ground current storage temperature dynamic power dissipation Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V active mode high-impedance mode VO = −0.5 V to 7.0 V [1] [1] [1] [1] [1] [1] [1] Min −0.5 −20 −0.5 −0.5 −25 −50 −65 - Max 7.0 ±20 VCC + 0.5 7.0 50 +150 300 Unit V mA mA V V mA mA mA °C mW Tamb = −40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 3 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions Min 2.0 0 0 −40 74HC3G07 Typ 5.0 +25 1.67 Max 6.0 6.0 VCC +125 625 139 83 Min 4.5 0 0 −40 74HCT3G07 Typ 5.0 +25 1.67 Max 5.5 5.5 VCC +125 139 V V V °C ns/V ns/V ns/V Unit 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter 74HC3G07 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ILO ICC CI input leakage current output leakage current supply current input capacitance VI = VCC or GND; VCC = 6.0 V VI = VIH; VO = VCC or GND per input pin; VCC = 6.0 V; VI = VCC or GND; IO = 0 A; 0 0 0 0.15 0.16 1.5 0.1 0.1 0.1 0.33 0.33 ±0.1 ±5.0 10 0.1 0.1 0.1 0.4 0.4 ±1.0 ±10 20 V V V V V µA µA µA pF 1.5 3.15 4.2 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V Conditions −40 °C to +85 °C Min Typ[1] Max −40 °C to +125 °C Min Max Unit 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 4 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter 74HCT3G07 VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL IO = 20 µA; VCC = 4.5 V IO = 4.0 mA; VCC = 4.5 V II ILO ICC ∆ICC CI [1] Conditions −40 °C to +85 °C Min 2.0 Typ[1] 1.6 1.2 Max 0.8 −40 °C to +125 °C Min 2.0 Max 0.8 Unit V V - 0 0.15 1.5 0.1 0.33 ±1.0 ±5.0 10 375 - - 0.1 0.4 ±1.0 ±10 20 410 - V V µA µA µA µA pF input leakage current output leakage current supply current additional supply current input capacitance VI = VCC or GND; VCC = 5.5 V VI = VIH; VO = VCC or GND per input pin; VCC = 5.5 V; VI = VCC or GND; IO = 0 A; per input; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; IO = 0 A Typical values are measured at Tamb = 25 °C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 °C; for test circuit see Figure 7. Symbol Parameter 74HC3G07 tPZL OFF-state to LOW propagation delay nA to nY; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPLZ LOW to OFF-state propagation delay nA to nY; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTHL HIGH to LOW output nY; see Figure 6 transition time VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance VI = GND to VCC [1] Conditions −40 °C to +85 °C Min Typ Max −40 °C to +125 °C Min Max Unit - 25 9 7 25 11 10 18 6 5 4 95 19 16 95 23 23 95 19 16 - - 125 25 20 125 30 26 125 25 20 - ns ns ns ns ns ns ns ns ns pF 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 5 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 °C; for test circuit see Figure 7. Symbol Parameter 74HCT3G07 tPZL tPLZ tTHL CPD OFF-state to LOW propagation delay LOW to OFF-state propagation delay nA to nY; see Figure 6 VCC = 4.5 V nA to nY; see Figure 6 VCC = 4.5 V [1] Conditions −40 °C to +85 °C Min Typ Max −40 °C to +125 °C Min Max Unit - 11 10 6 4 27 26 19 - 32 31 22 - ns ns ns pF HIGH to LOW output VCC = 4.5 V; see Figure 6 transition time power dissipation capacitance VI = GND to VCC − 1.5 V - [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 12. Waveforms VI nA input GND tPLZ VCC nY output VOL VX tTHL 001aak034 VM tPZL VM Measurement points are given in Table 9. VOL is the typical output voltage level that occurs with the output load. Fig 6. The input (nA) to output (nY) propagation delays Table 9. Type 74HC3G07 74HCT3G07 Measurement points Input VM 0.5 × VCC 1.3 V Output VM 0.5 × VCC 1.3 V VX 0.1 × VCC 0.1 × VCC 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 6 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7. Table 10. Type Test circuit for measuring switching times Test data Input VI tr, tf ≤ 6 ns ≤ 6 ns GND to VCC GND to 3 V Load CL 50 pF 50 pF RL 1 kΩ 1 kΩ S1 position tPZL, tPLZ VCC VCC 74HC3G07 74HCT3G07 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 7 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 8. Package outline SOT505-2 (TSSOP8) © NXP B.V. 2009. All rights reserved. 74HC_HCT3G07_2 Product data sheet Rev. 02 — 12 May 2009 8 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 9. Package outline SOT765-1 (VSSOP8) © NXP B.V. 2009. All rights reserved. 74HC_HCT3G07_2 Product data sheet Rev. 02 — 12 May 2009 9 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 10. Package outline SOT996-2 (XSON8U) 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 10 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs 14. Abbreviations Table 11. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 12. Revision history Release date 20090512 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT3G07_1 Document ID 74HC_HCT3G07_2 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74HC3G07GD and 74HCT3G07GD (XSON8U package) Product specification - 74HC_HCT3G07_1 20031015 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 11 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT3G07_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 12 May 2009 12 of 13 NXP Semiconductors 74HC3G07; 74HCT3G07 Triple buffer with open-drain outputs 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 May 2009 Document identifier: 74HC_HCT3G07_2