74HCT4020N,652

74HC4020; 74HCT4020 14-stage binary ripple counter Rev. 5 — 6 August 2012 Product data sheet 1. General description The 74HC4020; 74HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4020B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4020; 74HCT4020 are 14-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0, Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. 2. Features and benefits  Multiple package options  Complies with JEDEC standard no. 7A  Specified from 40 C to +85 C and from 40 C to +125 C 3. Applications  Frequency dividing circuits  Time delay circuits  Control counters 4. Ordering information Table 1. Ordering information Type number 74HC4020N Package Temperature range Name Description Version 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body SOT338-1 width 5.3 mm 74HCT4020N 74HC4020D 74HCT4020D 74HC4020DB 74HCT4020DB 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter Table 1. Ordering information …continued Type number 74HC4020PW Package Temperature range Name Description Version 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm 74HCT4020PW 74HC4020BQ 74HCT4020BQ 5. Functional diagram CP MR 10 11 T 14-STAGE COUNTER CD 9 7 5 4 6 13 12 14 15 1 2 3 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aal201 Fig 1. Functional diagram CTR14 10 11 CP MR Q0 9 10 + Q3 7 11 CT = 0 Q4 5 5 Q5 4 4 Q6 6 6 Q7 13 Q8 12 Q9 14 14 Q10 15 15 Q11 1 1 Q12 2 Q13 3 Logic symbol 74HC_HCT4020 Product data sheet 9 7 13 CT 12 2 13 3 001aal203 001aal202 Fig 2. 0 Fig 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 2 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter Q Q FF T 1 CP FF T 2 Q Q Q RD Q FF T 3 RD Q FF T 4 Q FF T 6 Q RD Q RD RD MR Q0 Q3 Q13 001aal204 Fig 4. Logic diagram 6. Pinning information 6.1 Pinning terminal 1 index area 1 74HC4020 74HCT4020 16 VCC Q11 74HC4020 74HCT4020 Q12 2 15 Q10 14 Q9 Q11 1 16 VCC Q13 3 Q12 2 15 Q10 Q5 4 13 Q7 Q13 3 14 Q9 Q4 5 12 Q8 Q5 4 13 Q7 Q6 6 Q4 5 12 Q8 Q3 7 Q6 6 11 MR Q3 7 10 CP GND 8 8 9 Q0 Q0 11 MR 10 CP GND 9 VCC(1) 001aal206 Transparent top view 001aal205 (1) The substrate is attached to this pad using conductive die attach material. It cannot be used as supply pin or input. It is recommended that no connection is made at all. Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 6.2 Pin description Table 2. Pin description Symbol Pin Description Q0, Q3 to Q13 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 output GND 8 ground (0 V) CP 10 clock input (HIGH-to-LOW, edge-triggered) MR 11 master reset input (active HIGH) VCC 16 positive supply voltage 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 3 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter 7. Functional description Table 3. Function table Input Output CP MR Q0, Q3 to Q13  L no change  L count X H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition. 7.1 Timing diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 CP input MR input Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aal207 Fig 7. Timing diagram 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 4 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C DIP16 package - 750 mW SO16, SSOP16, TSSOP16 and DHVQFN16 packages - 500 mW [1] Tamb = 40 C to +125 C total power dissipation Ptot [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions 74HC4020 74HCT4020 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V t/V input transition rise and fall rate Tamb ambient temperature 74HC_HCT4020 Product data sheet except for Schmitt trigger inputs VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 40 +25 +125 40 +25 +125 All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 C © NXP B.V. 2012. All rights reserved. 5 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V 74HC4020 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V VI = VIH or VIL IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - - - - - pF 74HCT4020 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V - - 0.1 - 1 - 1 A VOL II input leakage current 74HC_HCT4020 Product data sheet VI = VCC or GND; VCC = 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 6 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ Max Min Max Min Max - - 8.0 - 80 - 160 A pin MR - 110 396 - 495 - 539 A pin CP - 85 306 - 383 - 417 A - 3.5 - - - - - pF ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V ICC additional supply current VI = VCC  2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V CI 40 C to +85 C 40 C to +125 C Unit input capacitance 11. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V; CL = 50 pF - 39 VCC = 4.5 V; CL = 50 pF - 14 140 - 28 - 175 - 210 ns 35 - 42 ns VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns VCC = 6.0 V; CL = 50 pF - 11 24 - 30 - 36 ns VCC = 2.0 V; CL = 50 pF - 22 75 - 95 - 110 ns VCC = 4.5 V; CL = 50 pF - 8 15 - 19 - 22 ns VCC = 5.0 V; CL = 15 pF - 6 - - - - - ns 74HC4020 tpd propagation delay [1] CP to Q0; see Figure 8 Qn to Qn+1; see Figure 9 tPHL tt VCC = 6.0 V; CL = 50 pF - 6 13 - 16 - 19 ns HIGH to LOW MR to Qn; see Figure 8 propagation VCC =2.0 V; CL = 50 pF delay VCC = 4.5 V; CL = 50 pF - 55 170 - 215 - 225 ns - 20 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V; CL = 50 pF - 16 29 - 37 - 43 ns VCC = 2.0 V; CL = 50 pF - 19 75 - 95 - 110 ns VCC = 4.5 V; CL = 50 pF - 7 15 - 19 - 22 ns VCC = 6.0 V; CL = 50 pF - 6 13 - 16 - 19 ns transition time 74HC_HCT4020 Product data sheet [2] Qn; see Figure 8 All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 7 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter tW 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V; CL = 50 pF 80 14 - 100 - 120 - ns VCC = 4.5 V; CL = 50 pF 16 4 - 20 - 24 - ns VCC = 6.0 V; CL = 50 pF 14 3 - 17 - 20 - ns VCC = 2.0 V; CL = 50 pF 80 17 - 100 - 120 - ns VCC = 4.5 V; CL = 50 pF 16 6 - 20 - 24 - ns VCC = 6.0 V; CL = 50 pF 14 5 - 17 - 20 - ns VCC = 2.0 V; CL = 50 pF 50 6 - 65 - 75 - ns VCC = 4.5 V; CL = 50 pF 10 2 - 13 - 15 - ns VCC = 6.0 V; CL = 50 pF 9 2 - 11 - 13 - ns VCC = 2.0 V; CL = 50 pF 6.0 30 - 4.8 - 4.0 - MHz VCC = 4.5 V; CL = 50 pF 30 92 - 24 - 20 - MHz VCC = 5.0 V; CL = 15 pF - 101 - - - - - MHz 35 109 - 28 - 24 - MHz - 19 - - - - - pF VCC = 4.5 V; CL = 50 pF - 18 36 - 45 - 54 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 4.5 V; CL = 50 pF - 8 15 - 19 - 22 ns VCC = 5.0 V; CL = 15 pF - 6 - - - - - ns HIGH to LOW MR to Qn; see Figure 8 propagation VCC = 4.5 V; CL = 50 pF delay VCC = 5.0 V; CL = 15 pF - 22 45 - 56 - 68 ns - 19 - - - - - ns - 7 15 - 19 - 22 ns 20 7 - 25 - 30 - ns 20 8 - 25 - 30 - ns 10 2 - 13 - 15 - ns pulse width CP HIGH or LOW; see Figure 8 MR HIGH; see Figure 8 trec fmax recovery time MR to CP; see Figure 8 maximum frequency see Figure 8 VCC = 6.0 V; CL = 50 pF CPD [3] power dissipation capacitance 74HCT4020 tpd propagation delay [1] CP to Q0; see Figure 8 Qn to Qn+1; see Figure 9 tPHL tt tW transition time Qn; see Figure 8 pulse width CP HIGH or LOW; see Figure 8 [2] VCC = 4.5 V; CL = 50 pF VCC = 4.5 V; CL = 50 pF MR HIGH; see Figure 8 VCC = 4.5 V; CL = 50 pF trec recovery time MR to CP; see Figure 8 VCC = 4.5 V; CL = 50 pF 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 8 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter fmax maximum frequency 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 4.5 V; CL = 50 pF 25 47 - 20 - 17 - MHz VCC = 5.0 V; CL = 15 pF - 52 - - - - - MHz - 20 - - - - - pF see Figure 8 [3] power dissipation capacitance CPD [1] 25 C Conditions tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz;  (CL  VCC2  fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 12. Waveforms VI VM MR input 1/fmax tW trec VI VM CP input tPHL tPLH tW 90 % Q0 or Qn output tPHL 90 % 10 % VM 10 % tTLH tTHL 001aad590 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Clock timing, propagation delays, pulse widths and measurement points 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 9 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter VOH Qn output VM VOL tPLH tPHL VOH VM Qn+1 output VOL 001aai120 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Waveforms showing the output Qn to output Qn+1 propagation delays Table 8. Measurement points Type Input Output VM VM 74HC4020 0.5  VCC 0.5  VCC 74HCT4020 1.3 V 1.3 V 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 10 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 10. Test circuit for measuring switching times Table 9. Test data Type Input VI Load tr, tf CL 74HC4020 VCC 6 ns 15 pF, 50 pF 74HCT4020 3V 6 ns 15 pF, 50 pF 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 11 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 11. Package outline SOT38-4 (DIP16) 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 12 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT109-1 (SO16) 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 13 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 13. Package outline SOT338-1 (SSOP16) 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 14 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 14. Package outline SOT403-1 (TSSOP16) 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 15 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 15. Package outline SOT763-1 (DHVQFN16) 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 16 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter 14. Abbreviations Table 10. Abbreviations Acronym Abbreviation CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4020 v.5 20120806 Product data sheet - 74HC_HCT4020 v.4 Modifications: 74HC_HCT4020 v.4 Modifications: 74HC_HCT4020 v.3 • Measurement points added to figure 8 (errata). 20111213 • Product data sheet - 74HC_HCT4020 v.3 Product data sheet - 74HC_HCT4020_CNV v.2 Product specification - - Legal pages updated. 20100120 74HC_HCT4020_CNV v.2 19970901 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 17 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT4020 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 18 of 20 74HC4020; 74HCT4020 NXP Semiconductors 14-stage binary ripple counter Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT4020 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 August 2012 © NXP B.V. 2012. All rights reserved. 19 of 20 NXP Semiconductors 74HC4020; 74HCT4020 14-stage binary ripple counter 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 August 2012 Document identifier: 74HC_HCT4020