74HCT4052PW

74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Rev. 06 — 11 January 2010 Product data sheet 1. General description The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A. The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The common channel select logics include two digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 and S1. VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E). The VCC to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the 74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). 2. Features Wide analog input voltage range from −5 V to +5 V Low ON resistance: 80 Ω (typical) at VCC − VEE = 4.5 V 70 Ω (typical) at VCC − VEE = 6.0 V 60 Ω (typical) at VCC − VEE = 9.0 V Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals Typical ‘break before make’ built-in Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information Package Temperature range 74HC4052 74HC4052D 74HC4052DB 74HC4052N 74HC4052PW 74HC4052BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO16 SSOP16 DIP16 TSSOP16 DHVQFN16 plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic dual in-line package; 16 leads (300 mil) plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic dual-in line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic dual in-line package; 16 leads (300 mil) plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic dual-in line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT109-1 SOT338-1 SOT38-4 SOT403-1 SOT763-1 Name Description Version Type number 74HCT4052 74HCT4052D 74HCT4052DB 74HCT4052N −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO16 SSOP16 DIP16 TSSOP16 DHVQFN16 SOT109-1 SOT338-1 SOT38-4 SOT403-1 SOT763-1 74HCT4052PW −40 °C to +125 °C 74HCT4052BQ −40 °C to +125 °C 5. Functional diagram 10 13 1Z 1Y0 10 9 S0 S1 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 6 E 2Z 001aah824 0 1 G4 4× 9 6 12 14 15 11 1 5 2 4 13 3 0 3 MDX 0 1 2 3 1 5 2 4 12 14 15 11 001aah825 2Y3 3 Fig 1. Logic symbol Fig 2. IEC logic symbol © NXP B.V. 2010. All rights reserved. 74HC_HCT4052_6 Product data sheet Rev. 06 — 11 January 2010 2 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer nYn VCC VEE VCC VCC VCC from logic VEE nZ VEE mnb043 Fig 3. Schematic diagram (one switch) VDD 16 13 12 1Z 1Y0 14 1Y1 15 S0 10 1Y2 11 9 LOGIC LEVEL CONVERSION 1-OF-4 DECODER 1 1Y3 S1 2Y0 E 6 5 2Y1 2 2Y2 4 2Y3 3 8 VSS 7 VEE 2Z 001aah872 Fig 4. Functional diagram © NXP B.V. 2010. All rights reserved. 74HC_HCT4052_6 Product data sheet Rev. 06 — 11 January 2010 3 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 74HC4052 74HCT4052 2Y0 2Y2 2Z 2Y3 2Y1 E VEE GND 1 2 3 4 5 6 7 8 001aah822 74HC4052 74HCT4052 16 VCC 15 1Y2 2Y2 14 1Y1 13 1Z 12 1Y0 11 1Y3 VEE 10 S0 9 S1 7 8 GND S1 9 2Z 2Y3 2Y1 E 2 3 4 5 6 VCC (1) terminal 1 index area 16 VCC 15 1Y2 14 1Y1 13 1Z 12 1Y0 11 1Y3 10 S0 1 2Y0 001aah823 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration for DIP16, SO16 and (T)SSOP16 Fig 6. Pin configuration for DHVQFN16 6.2 Pin description Table 2. Symbol 2Y0 2Y2 2Z 2Y3 2Y1 E VEE GND S1 S0 1Y3 1Y0 1Z 1Y1 1Y2 VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description independent input or output 2Y0 independent input or output 2Y2 common input or output 2 independent input or output 2Y3 independent input or output 2Y1 enable input (active LOW) negative supply voltage ground (0 V) select logic input 1 select logic input 0 independent input or output 1Y3 independent input or output 1Y0 common input or output 1 independent input or output 1Y1 independent input or output 1Y2 positive supply voltage 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 4 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 7. Functional description 7.1 Function table Table 3. Input E L L L L H [1] Function table[1] Channel on S1 L L H H X S0 L H L H X nY0 and nZ nY1 and nZ nY2 and nZ nY3 and nZ none H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VEE = GND (ground = 0 V). Symbol VCC IIK ISK ISW IEE ICC IGND Tstg Ptot P [1] Parameter supply voltage input clamping current switch clamping current switch current supply current supply current ground current storage temperature total power dissipation power dissipation Conditions [1] Min −0.5 −65 Max +11.0 ±20 ±20 ±25 ±20 50 −50 +150 500 100 Unit V mA mA mA mA mA mA °C mW mW VI < −0.5 V or VI > VCC + 0.5 V VSW < −0.5 V or VSW > VCC + 0.5 V −0.5 V < VSW < VCC + 0.5 V Tamb = −40 °C to +125 °C per switch [2] - To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE. For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. [2] 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 5 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 9. Recommended operating conditions Table 5. Symbol VCC Recommended operating conditions Parameter supply voltage Conditions Min see Figure 7 and Figure 8 VCC − GND VCC − VEE VI VSW Tamb Δt/ΔV input voltage switch voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 10.0 V 2.0 2.0 GND VEE −40 5.0 5.0 +25 1.67 1.67 1.67 1.67 10.0 10.0 VCC VCC +125 625 139 83 31 4.5 2.0 GND VEE −40 5.0 5.0 +25 1.67 1.67 1.67 1.67 5.5 10.0 VCC VCC +125 139 139 139 139 V V V V °C ns/V ns/V ns/V ns/V 74HC4052 Typ Max Min 74HCT4052 Typ Max Unit 12 VCC − GND (V) 8 mnb044 12 VCC − GND (V) 10 mnb045 8 operating area 6 operating area 4 4 2 0 0 4 8 VCC − VEE (V) 12 0 0 4 8 VCC − VEE (V) 12 Fig 7. Guaranteed operating area as a function of the supply voltages for 74HC4052 Fig 8. Guaranteed operating area as a function of the supply voltages for 74HCT4052 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 6 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 10. Static characteristics Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4052: VCC − GND or VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4052: VCC − GND = 4.5 V and 5.5 V, VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter °C[1] Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 μA VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA RON(rail) ON resistance (rail) Vis = VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 μA VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA Vis = VCC VCC = 2.0 V; VEE = 0 V; ISW = 100 μA VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA ΔRON ON resistance mismatch between channels Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V VCC = 4.5 V; VEE = 0 V VCC = 6.0 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V Tamb = −40 °C to +125 °C RON(peak) ON resistance (peak) Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 μA VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA [2] [2] [2] [2] Conditions Min Typ Max Unit Tamb = −40 °C to +85 RON(peak) ON resistance (peak) - 100 90 70 150 80 70 60 150 90 80 65 9 8 6 225 200 165 175 150 130 200 175 150 - Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω - - 270 240 195 Ω Ω Ω Ω 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 7 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 …continued VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4052: VCC − GND or VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4052: VCC − GND = 4.5 V and 5.5 V, VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol RON(rail) Parameter ON resistance (rail) Conditions Vis = VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 μA VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA Vis = VCC VCC = 2.0 V; VEE = 0 V; ISW = 100 μA VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA [1] [2] All typical values are measured at Tamb = 25 °C. When supply voltages (VCC − VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of 2 V, it is recommended to use these devices only for transmitting digital signals. [2] [2] Min - Typ - Max 210 180 160 240 210 180 Unit Ω Ω Ω Ω Ω Ω Ω Ω 100 RON (Ω) 80 (1) 001aai068 60 Vsw (2) V 40 VCC from select input Sn nYn Vis (3) nZ GND VEE Isw 20 0 0 001aah826 1.8 3.6 5.4 7.2 Vis (V) 9.0 Vis = 0 V to (VCC − VEE). Vis = 0 V to (VCC − VEE). (1) VCC = 4.5 V (2) VCC = 6 V (3) VCC = 9 V V sw R ON = -------I sw Fig 9. Test circuit for measuring RON Fig 10. Typical RON as a function of input voltage Vis 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 8 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Table 7. Static characteristics for 74HC4052 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol VIH Parameter °C[1] VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V II input leakage current VEE = 0 V; VI = VCC or GND VCC = 6.0 V VCC = 10.0 V IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 11 per channel all channels IS(ON) ICC ON-state leakage current supply current VI = VIH or VIL; |VSW| = VCC − VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 6.0 V VCC = 10.0 V CI Csw input capacitance switch capacitance independent pins nYn common pins nZ Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 9.0 V II input leakage current VEE = 0 V; VI = VCC or GND VCC = 6.0 V VCC = 10.0 V ±1.0 ±2.0 μA μA 1.5 3.15 4.2 6.3 0.5 1.35 1.8 2.7 V V V V V V V V 3.5 5 12 80.0 160.0 μA μA pF pF pF ±1.0 ±2.0 ±2.0 μA μA μA ±1.0 ±2.0 μA μA 1.5 3.15 4.2 6.3 1.2 2.4 3.2 4.7 0.8 2.1 2.8 4.3 0.5 1.35 1.8 2.7 V V V V V V V V HIGH-level input voltage Conditions Min Typ Max Unit Tamb = −40 °C to +85 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 9 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Table 7. Static characteristics for 74HC4052 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol IS(OFF) Parameter OFF-state leakage current Conditions VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 11 per channel all channels IS(ON) ICC ON-state leakage current supply current VI = VIH or VIL; |VSW| = VCC − VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 6.0 V VCC = 10.0 V [1] All typical values are measured at Tamb = 25 °C. Min Typ Max Unit - - ±1.0 ±2.0 ±2.0 μA μA μA - - 160.0 320.0 μA μA Table 8. Static characteristics for 74HCT4052 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol VIH VIL II IS(OFF) Parameter HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current Conditions VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VCC or GND; VCC = 5.5 V; VEE = 0 V VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 11 per channel all channels IS(ON) ICC ON-state leakage current supply current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 12 VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 5.5 V; VEE = 0 V VCC = 5.0 V; VEE = −5.0 V ΔICC CI Csw additional supply current input capacitance switch capacitance independent pins nYn common pins nZ Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 V per input; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V 45 3.5 5 12 80.0 160.0 202.5 μA μA μA pF pF pF ±1.0 ±2.0 ±2.0 μA μA μA Min 2.0 Typ 1.6 1.2 Max 0.8 ±1.0 Unit V V μA Tamb = −40 °C to +85 °C[1] 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 10 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Table 8. Static characteristics for 74HCT4052 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol VIL ILI IS(OFF) Parameter LOW-level input voltage input leakage current OFF-state leakage current Conditions VCC = 4.5 V to 5.5 V VI = VCC or GND; VCC = 5.5 V; VEE = 0 V VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 11 per channel all channels IS(ON) ICC ON-state leakage current supply current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 12 VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 5.5 V; VEE = 0 V VCC = 5.0 V; VEE = −5.0 V ΔICC additional supply current per input; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V 160.0 320.0 220.5 μA μA μA ±1.0 ±2.0 ±2.0 μA μA μA Min Typ Max 0.8 ±1.0 Unit V μA [1] All typical values are measured at Tamb = 25 °C. VCC from select input Sn Isw Isw A Vis nYn GND nZ VEE A Vos 001aah827 Vis = VCC and Vos = VEE. Vis = VEE and Vos = VCC. Fig 11. Test circuit for measuring OFF-state current HIGH from select input VCC Sn Isw A Vis nYn GND nZ VEE Vos 001aah828 Vis = VCC and Vos = open-circuit. Vis = VEE and Vos = open-circuit. Fig 12. Test circuit for measuring ON-state current 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 11 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 9. Dynamic characteristics for 74HC4052 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol tpd Parameter Conditions [2] Min Typ Max Unit Tamb = −40 °C to +85 °C[1] propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 VCC = 2.0 V; VEE = 0 V VCC = 4.5 V; VEE = 0 V VCC = 6.0 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V ton turn-on time E, Sn to Vos; RL = ∞ Ω; see Figure 14 VCC = 2.0 V; VEE = 0 V VCC = 4.5 V; VEE = 0 V VCC = 6.0 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V toff turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 VCC = 2.0 V; VEE = 0 V VCC = 4.5 V; VEE = 0 V VCC = 6.0 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V CPD power dissipation per switch; VI = GND to VCC capacitance propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 VCC = 2.0 V; VEE = 0 V VCC = 4.5 V; VEE = 0 V VCC = 6.0 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V ton turn-on time E, Sn to Vos; RL = ∞ Ω; see Figure 14 VCC = 2.0 V; VEE = 0 V VCC = 4.5 V; VEE = 0 V VCC = 6.0 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V [3] [5] [4] [3] - 14 5 4 4 105 38 30 26 74 27 22 22 57 75 15 13 10 405 81 69 58 315 63 54 48 - ns ns ns ns ns ns ns ns ns ns ns ns pF Tamb = −40 °C to +125 °C tpd [2] - - 90 18 15 12 490 98 83 69 ns ns ns ns ns ns ns ns 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 12 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Table 9. Dynamic characteristics for 74HC4052 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol toff Parameter turn-off time Conditions E, Sn to Vos; RL = 1 kΩ; see Figure 14 VCC = 2.0 V; VEE = 0 V VCC = 4.5 V; VEE = 0 V VCC = 6.0 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V [1] [2] [3] [4] [5] All typical values are measured at Tamb = 25 °C. tpd is the same as tPHL and tPLH. ton is the same as tPZH and tPZL. toff is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; Σ{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. [4] Min - Typ - Max 375 75 64 57 Unit ns ns ns ns Table 10. Dynamic characteristics for 74HCT4052 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol tpd Parameter Conditions [2] Min Typ Max Unit Tamb = −40 °C to +85 °C[1] propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V ton turn-on time E, Sn to Vos; RL = 1 kΩ; see Figure 14 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V toff turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V CPD power dissipation per switch; VI = GND to VCC − 1.5 V capacitance propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V [5] [4] [3] - 5 4 41 28 26 21 57 15 10 88 60 63 48 - ns ns ns ns ns ns pF Tamb = −40 °C to +125 °C tpd [2] - - 18 12 ns ns 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 13 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Table 10. Dynamic characteristics for 74HCT4052 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol ton Parameter turn-on time Conditions E, Sn to Vos; RL = 1 kΩ; see Figure 14 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V toff turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V [1] [2] [3] [4] [5] All typical values are measured at Tamb = 25 °C. tpd is the same as tPHL and tPLH. ton is the same as tPZH and tPZL. toff is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; Σ{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. [4] [3] Min - Typ - Max 105 72 75 57 Unit ns ns ns ns Vis input 50 % tPLH tPHL Vos output 50 % 001aad555 Fig 13. Input (Vis) to output (Vos) propagation delays 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 14 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer VI E, Sn inputs 0V tPLZ VM tPZL Vos output 10 % tPHZ 90 % Vos output tPZH 50 % 50 % switch ON switch OFF switch ON 001aae330 For 74HC4052: VM = 0.5 × VCC. For 74HCT4052: VM = 1.3 V. Fig 14. Turn-on and turn-off times VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC Vis PULSE GENERATOR VI DUT RT CL VCC Vos RL S1 open GND VEE 001aae382 Definitions for test circuit; see Table 11: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = Test selection switch. Fig 15. Test circuit for measuring AC performance 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 15 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer Table 11. Test Test data Input VI Vis pulse VCC VEE tr, tf at fmax other[1] 6 ns 6 ns 6 ns 50 pF 50 pF 50 pF 1 kΩ 1 kΩ 1 kΩ open VEE VCC < 2 ns < 2 ns < 2 ns Load CL RL S1 position tPHL, tPLH tPZH, tPHZ tPZL, tPLZ [1] [2] [2] [2] [2] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor. VI values: a) For 74HC4052: VI = VCC b) For 74HCT4052: VI = 3 V 12. Additional dynamic characteristics Table 12. Additional dynamic characteristics Recommended conditions and typical values; GND = 0 V; Tamb = 25 °C; CL = 50 pF. Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output. Symbol dsin Parameter sine-wave distortion Conditions fi = 1 kHz; RL = 10 kΩ; see Figure 16 Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = −2.25 V Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = −4.5 V fi = 10 kHz; RL = 10 kΩ; see Figure 16 Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = −2.25 V Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = −4.5 V αiso isolation (OFF-state) RL = 600 Ω; fi = 1 MHz; see Figure 17 VCC = 2.25 V; VEE = −2.25 V VCC = 4.5 V; VEE = −4.5 V Xtalk crosstalk between two switches/multiplexers; RL = 600 Ω; fi = 1 MHz; see Figure 18 VCC = 2.25 V; VEE = −2.25 V VCC = 4.5 V; VEE = −4.5 V Vct crosstalk voltage peak-to-peak value; between control and any switch; RL = 600 Ω; fi = 1 MHz; E or Sn square wave between VCC and GND; tr = tf = 6 ns; see Figure 19 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V f(−3dB) −3 dB frequency response RL = 50 Ω; see Figure 20 VCC = 2.25 V; VEE = −2.25 V VCC = 4.5 V; VEE = −4.5 V [1] [2] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω). Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 Ω). [2] [2] [1] [1] [1] [1] Min - Typ 0.04 0.02 0.12 0.06 −50 −50 Max - Unit % % % % dB dB - −60 −60 - dB dB - 110 220 170 180 - mV mV MHz MHz 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 16 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer VCC Sn 10 μF Vis nYn/nZ VEE nZ/nYn GND RL CL Vos dB 001aah829 Fig 16. Test circuit for measuring sine-wave distortion VCC Sn 0.1 μF Vis nYn/nZ VEE nZ/nYn GND RL CL Vos dB 001aah871 VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; RS = 1 kΩ. a. Test circuit 0 αiso (dB) −20 001aae332 −40 −60 −80 −100 10 102 103 104 105 fi (kHz) 106 b. Isolation (OFF-state) as a function of frequency Fig 17. Test circuit for measuring isolation (OFF-state) 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 17 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer VCC Sn 0.1 μF Vis RL nYn/nZ VEE nZ/nYn GND RL CL VCC Sn nYn/nZ RL nZ/nYn VEE GND RL CL Vos dB 001aah873 Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers 2RL VCC 2RL Sn, E nYn G 2RL Vct nZ VEE GND 2RL oscilloscope 001aah913 Fig 19. Test circuit for measuring crosstalk between control input and any switch 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 18 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer VCC Sn 10 μF Vis nYn/nZ VEE nZ/nYn GND RL CL Vos dB 001aah829 VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; RS = 1 kΩ. a. Test circuit 5 Vos (dB) 3 001aad551 1 −1 −3 −5 10 102 103 104 105 f (kHz) 106 b. Typical frequency response Fig 20. Test circuit for frequency response 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 19 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 8 A1 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ o 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 21. Package outline SOT109-1 (SO16) 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 20 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index θ Lp L 1 8 (A 3) A detail X wM e bp 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 22. Package outline SOT338-1 (SSOP16) 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 21 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 23. Package outline SOT38-4 (DIP16) 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 22 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 24. Package outline SOT403-1 (TSSOP16) 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 23 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 25. Package outline SOT763-1 (DHVQFN16) 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 24 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 14. Abbreviations Table 13. Acronym CMOS DUT ESD HBM MM Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 14. Revision history Release date 20100111 Data sheet status Product data sheet Product data sheet Product specification Product specification Change notice Supersedes 74HC_HCT4052_5 74HC_HCT4052_4 74HC_HCT4052_3 74HC_HCT4052_CNV_2 Document ID 74HC_HCT4052_6 Modifications: 74HC_HCT4052_5 74HC_HCT4052_4 74HC_HCT4052_3 74HC_HCT4052_CNV_2 • Added type number 74HCT4052PW (TSSOP16 / SOT403-1 package). 20080505 20041111 20030516 19901201 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 25 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 26 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 12 Additional dynamic characteristics . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Contact information. . . . . . . . . . . . . . . . . . . . . 26 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 January 2010 Document identifier: 74HC_HCT4052_6