74HCT4075PW,112

74HC4075; 74HCT4075 Triple 3-input OR gate Rev. 3 — 3 November 2016 Product data sheet 1. General description The 74HC4075; 74HCT4075 is a triple 3-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Complies with JEDEC standard no. 7A  Input levels:  For 74HC4075: CMOS level  For 74HCT4075: TTL level  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number 74HC4075D Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HCT4075D 74HCT4075DB 40 C to +125 C 74HC4075PW 74HCT4075PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HC4075; 74HCT4075 NXP Semiconductors Triple 3-input OR gate 4. Functional diagram  $  %  & <   •     $  %  & <   •    $  $  %  & <   •  < %   & DDD Fig 1. DDD DDD Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning +& +&7 +& +&7 $   9&& %   & $   9&& $   % %   & %   $ $   % %   $  < &   < &  <   <   < *1'   & *1'   < & DDD Fig 4. Pin configuration SO14 74HC_HCT4075 Product data sheet DDD Fig 5. Pin configuration SSOP14 and TSSOP14 All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 2 of 15 74HC4075; 74HCT4075 NXP Semiconductors Triple 3-input OR gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A 3, 1, 11 data input 1B, 2B, 3B 4, 2, 12 data input 1C, 2C, 3C 5, 8, 13 data input 1Y, 2Y, 3Y 6, 9, 10 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Inputs Outputs nA nB nC nY L L L L X X H H X H X H H X X H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW IIK SO14 and (T)SSOP14 packages [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 74HC_HCT4075 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 3 of 15 74HC4075; 74HCT4075 NXP Semiconductors Triple 3-input OR gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC4075 Min Typ 74HCT4075 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V 74HC4075 VIH VIL VOH VOL HIGH-level input voltage VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V LOW-level input voltage LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A - - 2.0 - 20 - 40 A II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V 74HC_HCT4075 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 4 of 15 74HC4075; 74HCT4075 NXP Semiconductors Triple 3-input OR gate Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT4075 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V 3.98 4.32 - 3.84 - 3.7 - V IO = 4.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A IO = 4.0 mA - 0 0.1 - 0.1 - 0.1 V - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; VCC = 5.5 V; IO = 0 A - - 2.0 - 20 - 40 A ICC additional per input pin; VI = VCC  2.1 V; supply current other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A - 150 540 - 675 - 735 A - 3.5 - - - - - pF nA, nB, nC inputs CI input capacitance 74HC_HCT4075 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 5 of 15 74HC4075; 74HCT4075 NXP Semiconductors Triple 3-input OR gate 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 28 100 125 150 VCC = 4.5 V - 10 20 25 30 ns VCC = 5.0 V; CL = 15 pF - 8 - - - ns - 8 17 21 26 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns - 6 13 16 19 ns - 28 - - - pF - 12 24 30 36 ns 74HC4075 propagation delay nA, nB, nC to nY; see Figure 6 tpd [1] VCC = 2.0 V VCC = 6.0 V transition time tt [2] see Figure 6 VCC = 6.0 V per package; VI = GND to VCC [3] propagation delay nA, nB, nC to nY; see Figure 6 [1] power dissipation capacitance CPD ns 74HCT4075 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF transition time tt power dissipation capacitance CPD - 10 - - - ns VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns per package; VI = GND to VCC  1.5 V [3] - 32 - - - pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching;  (CL  VCC2  fo) = sum of outputs. 74HC_HCT4075 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 6 of 15 74HC4075; 74HCT4075 NXP Semiconductors Triple 3-input OR gate 11. Waveforms 9, Q$Q%Q&LQSXW 90 *1' W3+/ 92+ W3/+ 9< 90 9; Q