74LV138PW

74LV138 3-to-8 line decoder/demultiplexer; inverting Rev. 03 — 15 November 2007 Product data sheet 1. General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive active LOW outputs (Y0 to Y7). There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The 74LV138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. 2. Features s s s s s s s s s s Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C s s NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 3. Ordering information Table 1. Ordering information Package Temperature range 74LV138N 74LV138D 74LV138DB 74LV138PW 74LV138BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name DIP16 SO16 SSOP16 TSSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT38-4 SOT109-1 SOT338-1 SOT403-1 SOT763-1 Type number DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 4. Functional diagram DX 1 1 2 3 A0 A1 A2 Y0 Y1 Y2 Y3 4 5 6 E1 E2 E3 Y4 Y5 Y6 Y7 mna370 0 1 15 14 13 12 11 10 9 7 4 5 6 & 1 2 3 1 2 4 X/Y 0 1 2 3 4 5 6 15 14 13 12 11 10 9 7 0 G 2 0 7 15 14 13 12 11 10 9 7 2 3 2 3 4 4 5 6 & 5 6 7 EN 7 mna371 (a) (b) Fig 1. Logic symbol Fig 2. IEC logic symbol 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 2 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting Y0 1 2 3 A0 A1 A2 3-to-8 DECODER ENABLE EXITING Y1 Y2 Y3 Y4 Y5 Y6 Y7 4 5 6 E1 E2 E3 mna372 15 14 13 12 11 10 9 7 Fig 3. Functional diagram 5. Pinning information 5.1 Pinning 74LV138 A0 A1 A2 E1 E2 E3 Y7 GND 1 2 3 4 16 VCC 15 Y0 A1 14 Y1 13 Y2 A2 E1 E2 E3 6 7 8 001aad033 terminal 1 index area 2 3 4 5 6 7 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 (1) 138 5 12 Y3 11 Y4 10 Y5 9 Y6 1 A0 VCC 8 11 Y4 10 Y5 Y7 GND Y6 9 001aah106 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 5. Pin configuration DHVQFN16 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 3 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 5.2 Pin description Table 2. Symbol A0 A1 A2 E1 E2 E3 GND Y0 to Y7 VCC Pin description Pin 1 2 3 4 5 6 8 15, 14, 13, 12, 11, 10, 9, 7 16 Description address input address input address input enable input (active LOW) enable input (active LOW) enable input (active HIGH) ground (0 V) output supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care Input E1 H X X L L L L L L L L E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H Output Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg 74LV138_3 Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] Min −0.5 −50 −65 Max +7.0 ±20 ±50 ±25 50 +150 Unit V mA mA mA mA mA °C © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 4 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Ptot Parameter total power dissipation DIP16 package SO16 package (T)SSOP16 package DHVQFN16 package [1] [2] [3] [4] [5] Conditions Tamb = −40 °C to +125 °C [2] [3] [4] [5] Min - Max 750 500 500 500 Unit mW mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 12 mW/K above 70 °C. Ptot derates linearly with 8 mW/K above 70 °C. Ptot derates linearly with 5.5 mW/K above 60 °C. Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO Tamb ∆t/∆V Parameter supply voltage[1] input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.0 V to 2.0 V VCC = 2.0 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 5.5 V [1] Conditions Min 1.0 0 0 −40 - Typ 3.3 +25 - Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V °C ns/V ns/V ns/V ns/V The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 74LV138_3 −40 °C to +85 °C Min 0.9 1.4 2.0 0.7VCC Typ[1] Max 0.3 0.6 0.8 0.3VCC −40 °C to +125 °C Unit Min 0.9 1.4 2.0 0.7VCC Max 0.3 0.6 0.8 V V V V V V V 0.3VCC V © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 5 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH HIGH-level output voltage Conditions VI = VIH or VIL lO = −100 µA; VCC = 1.2 V lO = −100 µA; VCC = 2.0 V lO = −100 µA; VCC = 2.7 V lO = −100 µA; VCC = 3.0 V lO = −100 µA; VCC = 4.5 V lO = −6 mA; VCC = 3.0 V lO = −12 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.2 V IO = 100 µA; VCC = 2.0 V IO = 100 µA; VCC = 2.7 V IO = 100 µA; VCC = 3.0 V IO = 100 µA; VCC = 4.5 V IO = 6 mA; VCC = 3.0 V IO = 12 mA; VCC = 4.5 V II ICC ∆ICC CI [1] −40 °C to +85 °C Min 1.8 2.5 2.8 4.3 2.4 3.6 Typ[1] 1.2 2.0 2.7 3.0 4.5 2.82 4.2 0 0 0 0 0 0.25 0.35 3.5 Max 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 - −40 °C to +125 °C Unit Min 1.8 2.5 2.8 4.3 2.2 3.5 Max 0.2 0.2 0.2 0.2 0.50 0.65 1.0 160 850 V V V V V V V V V V V V V V µA µA µA pF input leakage current supply current additional supply current input capacitance VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V Typical values are measured at Tamb = 25 °C. 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 6 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 8. Symbol Parameter tpd propagation delay Conditions An to Yn; see Figure 6 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V E3, En to Yn; see Figure 6 and Figure 7 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] [3] [3] [3] [3] [2] −40 °C to +85 °C Min Typ[1] 75 26 19 12 15 Max 44 31 26 17 −40 °C to +125 °C Min Max 55 39 32 22 Unit ns ns ns ns ns ns - 75 26 19 14 15 45 43 30 25 19 - - 53 38 31 24 - ns ns ns ns ns ns pF [1] [2] [3] [4] All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. Typical values are measured at nominal supply voltage (VCC = 3.3 V). CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 7 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 11. Waveforms VCC An, E3 input GND VM tPHL VOH Yn output VOL VM tPLH 001aah080 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The inputs An, E3 to outputs Yn propagation delays VCC E1, E2 input GND tPHL VOH Yn output VOL VM 001aah081 VM tPLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. The inputs En to outputs Yn propagation delays Table 8. VCC < 2.7 V 2.7 V to 3.6 V ≥ 4.5 V Measurement points Input VM 0.5VCC 1.5 V 0.5VCC Output VM 0.5VCC 1.5 V 0.5VCC Supply voltage 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 8 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 1 kΩ VO 001aaa663 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 8. Load circuit for switching times Table 9. VCC < 2.7 V 2.7 V to 3.6 V ≥ 4.5 V Test data Input VI VCC 2.7 V VCC tr, tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Supply voltage 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 9 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 9. Package outline SOT38-4 (DIP16) 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 10 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 11 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT338-1 (SSOP16) 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 12 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 12. Package outline SOT403-1 (TSSOP16) 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 13 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT763-1 (DHVQFN16) 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 14 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. 74LV138_3 Modifications: Revision history Release date 20071115 Data sheet status Product data sheet Change notice Supersedes 74LV138_2 Document ID • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN16 package added. Section 8: derating values added for DHVQFN16 package. Section 12: outline drawing added for DHVQFN16 package. Product specification Product specification 74LV138_1 - 74LV138_2 74LV138_1 19980428 19970203 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 15 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LV138_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 15 November 2007 16 of 17 NXP Semiconductors 74LV138 3-to-8 line decoder/demultiplexer; inverting 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 November 2007 Document identifier: 74LV138_3