74LV174DB,112

INTEGRATED CIRCUITS 74LV174 Hex D-type flip-flop with reset; positive-edge trigger Product specification Supersedes data of 1997 Apr 07 IC24 Data Handbook
     1998 May 20 Philips Semiconductors Product specification 74LV174 Hex D-type flip-flop with reset; positive edge-trigger FEATURES DESCRIPTION • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce)  0.8V @ VCC = 3.3V, The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174. The 74LV174 has six edge–triggered D–type flip–flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip–flops simultaneously. Tamb = 25°C • Typical VOHV (output VOH undershoot)  2V @ VCC = 3.3V, The register is fully edge–triggered. The state of each D input, one set–up time prior to the LOW–to–HIGH clock transition, is transferred to the corresponding output of the flip–flop. Tamb = 25°C • Output capability: standard • ICC category: MSI A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT 16 13 ns tPHL/tPLH Propagation delay CP to Qn MR to Qn fmax Maximum clock frequency 77 MHz CI Input capacitance 3.5 pF CPD Power dissipation capacitance per flip-flop 17 pF CL = 15pF VCC = 3.3V VCC = 3.3V Notes 1 and 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD
VCC2 x fi 
(CL
VCC2
fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V;
(CL
VCC2
fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40°C to +125°C 74LV174 N 74LV174 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV174 D 74LV174 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV174 DB 74LV174 DB SOT338-1 16-Pin Plastic TSSOP –40°C to +125°C 74LV174 PW 74LV174PW DH SOT403-1 1998 May 20 2 853–1964 19422 Philips Semiconductors Product specification 74LV174 Hex D-type flip-flop with reset; positive edge-trigger PIN CONFIGURATION LOGIC SYMBOL 9 MR 1 16 VCC Q0 2 15 Q5 3 D0 Q0 2 D0 3 14 D5 4 D1 Q1 5 D1 4 13 D4 6 D2 Q2 7 Q4 11 D3 Q3 10 13 D4 Q4 12 14 D5 Q5 15 Q1 5 12 D2 6 11 D3 Q2 7 10 Q3 GND 8 9 CP CP MR 1 SV00347 SV00348 PIN DESCRIPTION PIN NUMBER 1 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 LOGIC SYMBOL (IEEE/IEC) SYMBOL FUNCTION MR Asynchronous master reset (active LOW) Q0 to Q5 Flip-flop outputs 9 1 C1 R D0 to D5 Data inputs 8 GND Ground (0V) 3 9 CP Clock input (LOW-to-HIGH, edgetriggered) 4 5 16 VCC Positive supply voltage 6 7 1D 2 11 10 13 12 14 15 SV00349 1998 May 20 3 Philips Semiconductors Product specification 74LV174 Hex D-type flip-flop with reset; positive edge-trigger FUNCTIONAL DIAGRAM FUNCTION TABLE INPUTS OPERATING MODES OUTPUTS MR CP Dn Q0 Reset (clear) L X X L 3 D0 Q0 2 Load ‘1’ H ↑ h H 4 D1 Q1 5 Load ‘0’ H ↑ l L 6 D2 Q2 7 Q3 10 FF1 to FF6 H h 11 D3 13 D4 Q4 12 L l 14 D5 Q5 15 q 1 MR 9 CP ↑ = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = Lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition = LOW–to–HIGH clock transition SV00350 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. See Note1 DC supply voltage MAX UNIT 1.0 3.3 5.5 V VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 50 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V –40 –40 – – – – – – – NOTES: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 May 20 4 Philips Semiconductors Product specification 74LV174 Hex D-type flip-flop with reset; positive edge-trigger ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) RATING UNIT –0.5 to +7.0 V VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA ±IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 mA ±IGND, ±ICC DC VCC or GND current for types with –standard outputs 50 mA Tstg Storage temperature range –65 to +150 °C PTOT Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) SYMBOL PARAMETER CONDITIONS VCC DC supply voltage ±IIK DC input diode current ±IOK for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 HIGH level output voltage; g STANDARD outputs LOW level output voltage all outputs out uts voltage; VOL LOW level output voltage; g STANDARD outputs 1998 May 20 MIN 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC UNIT MAX V 0.7*VCC VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2V; VI = VIH or VIL; –IO = 100µA VOH MAX VCC = 1.2V VCC = 4.5 to 5.5 HIGH level output voltage out uts voltage; all outputs -40°C to +125°C V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5V;VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0V;VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 VCC = 4.5V;VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50 V V VCC = 1.2V; VI = VIH or VIL; IO = 100µA VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 VCC = 4.5V;VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65 V V 5 Philips Semiconductors Product specification 74LV174 Hex D-type flip-flop with reset; positive edge-trigger DC CHARACTERISTICS FOR THE LV FAMILY (Continued) Over recommended operating conditions voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER LIMITS TEST CONDITIONS -40°C to +85°C -40°C to +125°C UNIT Input leakage current VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; MSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL tPHL/tPLH tPHL tW tW trem tsu 1998 May 20 PARAMETER Propagation delay CP to Qn Propagation delay MR to Qn Clock pulse width HIGH to LOW Master reset pulse width LOW Removal time MR to CP Set-up Set up time Dn to CP WAVEFORM Figure 1 Figure 2 Figure 1 Figure 2 Figure 2 Figure 3 LIMITS –40 to +85 °C CONDITION VCC(V) MIN TYP1 1.2 – 2.0 – LIMITS –40 to +125 °C MAX MIN 100 – – – 34 43 – 53 2.7 – 25 31 – 39 3.0 to 3.6 – 192 25 – 31 4.5 to 5.5 – 133 21 – 26 1.2 – 80 – – – 2.0 – 27 43 – 53 2.7 – 20 31 – 39 3.0 to 3.6 – 152 25 – 31 4.5 to 5.5 – 113 21 – 26 2.0 34 10 – 41 – 2.7 25 8 – 30 – 3.0 to 3.6 20 62 – 24 – 4.5 to 5.5 13 43 2.0 34 9 – 41 – 2.7 25 6 – 30 – 3.0 to 3.6 20 5 – 24 – 4.5 to 5.5 13 42 1.2 – –20 – – – 2.0 5 –7 – 5 – 2.7 5 –5 – 5 – 3.0 to 3.6 5 –42 – 5 – 4.5 to 5.5 5 –33 1.2 – 10 – – – 2.0 22 4 – 26 – 2.7 16 3 – 19 – 3.0 to 3.6 13 22 – 15 – 4.5 to 5.5 9 13 6 UNIT MAX ns ns ns 16 ns 16 ns 5 10 ns Philips Semiconductors Product specification 74LV174 Hex D-type flip-flop with reset; positive edge-trigger AC CHARACTERISTICS (Continued) GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER Hold time Dn to CP th Figure 1 LIMITS –40 to +85 °C CONDITION LIMITS –40 to +125 °C VCC(V) MIN TYP1 MAX MIN MAX 1.2 – –10 – – – 2.0 5 –4 – 5 – 2.7 5 –2 – 5 – 3.0 to 3.6 5 –22 – 5 – 4.5 to 5.5 5 –13 2.0 14 40 – 12 – 2.7 19 58 – 16 – 3.0 to 3.6 24 702 – 20 – 4.5 to 5.5 36 1003 Figure 3 Maximum clock pulse frequency fmax WAVEFORM UNIT ns 5 MHz 30 NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. AC WAVEFORMS VM = 1.5V at VCC  2.7V  3.6V VM = 0.5V * VCC at VCC
2.7V and  4.5V VOL and VOH are the typical output voltage drop that occur with the output load. Vi MR INPUT VM GND tw trem 1/fmax Vi VI VM CP INPUT CP INPUT VM GND GND tPHL tw tPLH VOH tPHL Qn OUTPUT VOH Qn OUTPUT VM VM VOL VOL SV00352 Figure 2. The master reset (MR) pulse width, the master reset to output (Qn) propagation delay and the master reset to clock removal time. SV00351 Figure 1. The clock (CP) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency. 1998 May 20 7 Philips Semiconductors Product specification 74LV174 Hex D-type flip-flop with reset; positive edge-trigger AC WAVEFORMS (Continued) TEST CIRCUIT VM = 1.5V at VCC  2.7V  3.6V VM = 0.5V * VCC at VCC
2.7V and  4.5V VOL and VOH are the typical output voltage drop that occur with the output load. Vcc VO Vl PULSE GENERATOR D.U.T. Vl 50pF RT CP INPUT CL RL= 1k VM GND t su Vl Dn INPUT GND VOH Test Circuit for Outputs t su ÌÌÌÌ ÌÌÌÌÌ ÌÌ ÌÌÌÌ ÌÌÌÌÌ ÌÌ ÌÌÌÌ ÌÌÌÌÌ ÌÌ th Qn OUTPUT th DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitiance VM RT = Termination resistance should be equal to ZOUT of pulse generators. TEST tPLH/tPHL VM VOL VCC VI < 2.7V VCC 2.7–3.6V 2.7V ≥ 4.5 V VCC SV00902 Figure 4. SV00353 Figure 3. Data set-up and hold times for the data input (Dn). NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. 1998 May 20 8 Load circuitry for switching times Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive edge-trigger DIP16: plastic dual in-line package; 16 leads (300 mil) 1998 May 20 9 74LV174 SOT38-4 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive edge-trigger SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 May 20 10 74LV174 SOT109-1 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive edge-trigger SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 May 20 11 74LV174 SOT338-1 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive edge-trigger TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 May 20 12 74LV174 SOT403-1 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive edge-trigger NOTES 1998 May 20 13 74LV174 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive edge-trigger 74LV174 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number:
     1997 Apr 07 14 Date of release: 05-96 9397-750-04433