74LV244PW,112

74LV244 Octal buffer/line driver (3-state) Rev. 3 — 11 March 2014 Product data sheet 1. General description The 74LV244 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC244 and 74HCT244. The 74LV244 is an octal non-inverting buffer/line driver with 3-state outputs. The output enable inputs 1OE and 2OE control the 3-state outputs. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74LV244 is identical to the 74LV240 but has non-inverting outputs. 2. Features and benefits        Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V; Tamb = 25 C Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V; Tamb = 25 C Complies with JEDEC standard no. 7A ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV244N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 74LV244D 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LV244DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm 74LV244PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT339-1 SOT360-1 74LV244 NXP Semiconductors Octal buffer/line driver (3-state) 4. Block diagram           $