74LV259D

74LV259 8-bit addressable latch Rev. 03 — 2 January 2008 Product data sheet 1. General description The 74LV259 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The 74LV259 is multifunctional device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The 74LV259 also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the (D) input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the 74LV259 as an address latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. 2. Features s s s s s s s s s s s s Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C Combines demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C s s NXP Semiconductors 74LV259 8-bit addressable latch 3. Ordering information Table 1. Ordering information Package Temperature range 74LV259N 74LV259D 74LV259DB 74LV259PW 74LV259BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name DIP16 SO16 SSOP16 TSSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT38-4 SOT109-1 SOT338-1 SOT403-1 SOT763-1 Type number DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 4. Functional diagram 15 13 G8 Z9 14 DX 0 9,10D 1 C10 8R 4 LE 13 D Q0 Q1 Q2 Q3 4 5 6 7 9 10 11 12 1 2 3 14 0 G 2 0 7 1 2 3 4 5 6 7 5 6 7 9 10 11 12 001aah119 1 2 3 A0 A1 A2 MR 15 Q4 Q5 Q6 Q7 001aah118 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 2 of 19 NXP Semiconductors 74LV259 8-bit addressable latch Q0 Q1 1 2 3 A0 A1 A2 8 LATCHES 1 OF 8 DECODER Q2 Q3 Q4 Q5 14 15 13 LE MR D Q6 Q7 4 5 6 7 9 10 11 12 001aah120 Fig 3. Functional diagram 5. Pinning information 5.1 Pinning 74LV259 terminal 1 index area 16 VCC 15 MR 14 LE 13 D 12 Q7 VCC 8 (1) 74LV259 A0 A1 A2 Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 8 001aah127 A1 16 VCC 15 MR 14 LE 13 D 12 Q7 11 Q6 10 Q5 9 Q4 A2 Q0 Q1 Q2 Q3 2 3 4 5 6 7 GND Q4 9 1 A0 11 Q6 10 Q5 001aah117 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 5. Pin configuration DHVQFN16 5.2 Pin description Table 2. Symbol A0 A1 A2 GND Q[0:7] 74LV259_3 Pin description Pin 1 2 3 8 4, 5, 6, 7, 9, 10, 11, 12 Description address input address input address input ground (0 V) latch output © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 3 of 19 NXP Semiconductors 74LV259 8-bit addressable latch Table 2. Symbol D LE MR VCC Pin description …continued Pin 13 14 15 16 Description data input latch enable input (active LOW) conditional reset input (active LOW) supply voltage 6. Functional description Table 3. Mode select table H = HIGH voltage level; L = LOW voltage level LE L H L H MR H H L L Mode addressable latch memory active HIGH 8-channel demultiplexer reset Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = High or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = state of the output established during the last cycle in which it was addressed or cleared Operating modes master reset demultiplex (active HIGH) decoder (when D = H) Input MR L L L L L L L L L store (do nothing) addressable latch H H H H H H H H H LE H L L L L L L L L H L L L L L L L L D X d d d d d d d d X d d d d d d d H A0 X L H L H L H L H X L H L H L H L H A1 X L L H H L L H H X L L H H L L H H A2 X L L L L H H H H X L L L L H H H H Output Q0 L Q=d L L L L L L L q0 Q=d q0 q0 q0 q0 q0 q0 q0 Q1 L L Q=d L L L L L L q1 q1 Q=d q1 q1 q1 q1 q1 q1 Q2 L L L Q=d L L L L L q2 q2 q2 Q=d q2 q2 q2 q2 q2 Q3 L L L L Q=d L L L L q3 q3 q3 q3 Q=d q3 q3 q3 q3 Q4 L L L L L Q=d L L L q4 q4 q4 q4 q4 Q=d q4 q4 q4 Q5 L L L L L L Q=d L L q5 q5 q5 q5 q5 q5 q5 q5 Q=d L q6 q6 q6 q6 q6 q6 Q=d q6 Q6 L L L L L L Q7 L L L L L L L L Q=d q7 q7 q7 q7 q7 q7 q7 q7 Q=d Q = d q6 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 4 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C DIP16 package SO16 package (T)SSOP16 package DHVQFN16 package [1] [2] [3] [4] [5] [2] [3] [4] [5] Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] Min −0.5 −50 −65 - Max +4.6 ±20 ±50 ±25 50 +150 750 500 500 500 Unit V mA mA mA mA mA °C mW mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 12 mW/K above 70 °C. Ptot derates linearly with 8 mW/K above 70 °C. Ptot derates linearly with 5.5 mW/K above 60 °C. Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO Tamb ∆t/∆V Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.0 V to 2.0 V VCC = 2.0 V to 2.7 V VCC = 2.7 V to 3.6 V [1] Conditions [1] Min 1.0 0 0 −40 - Typ 3.3 +25 - Max 3.6 VCC VCC +125 500 200 100 Unit V V V °C ns/V ns/V ns/V The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 5 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 9. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VIL LOW-level input voltage VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.2 V IO = −100 µA; VCC = 2.0 V IO = −100 µA; VCC = 2.7 V IO = −100 µA; VCC = 3.0 V IO = −6 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.2 V IO = 100 µA; VCC = 2.0 V IO = 100 µA; VCC = 2.7 V IO = 100 µA; VCC = 3.0 V IO = 6 mA; VCC = 3.0 V II ICC ∆ICC CI [1] −40 °C to +85 °C Min 0.9 1.4 2.0 1.8 2.5 2.8 2.4 Typ[1] 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 3.5 Max 0.3 0.6 0.8 0.2 0.2 0.2 0.40 1.0 20.0 500 - −40 °C to +125 °C Unit Min 0.9 1.4 2.0 1.8 2.5 2.8 2.2 Max 0.3 0.6 0.8 0.2 0.2 0.2 0.50 1.0 160 850 V V V V V V V V V V V V V V V V µA µA µA pF input leakage current supply current additional supply current input capacitance VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V Typical values are measured at Tamb = 25 °C. 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 6 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; For test circuit see Figure 12. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 105 36 26 17 20 105 36 26 17 20 100 34 25 16 19 90 31 23 14 17 10 8 6 10 8 6 Max 49 36 29 49 36 29 48 35 28 43 31 25 - −40 °C to +125 °C Min 41 30 24 41 30 24 Max 61 45 36 61 45 36 60 44 35 53 39 31 - Unit propagation delay D to Qn; see Figure 8 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V [3] [3] [2] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns - tpd propagation delay An to Qn; see Figure 7 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V [3] [3] [2] - tpd propagation delay LE to Qn; Figure 6 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V [3] [3] - tPHL HIGH to LOW MR to Qn; Figure 9 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V [3] [3] propagation delay VCC = 1.2 V 34 25 tW pulse width LE, HIGH or LOW; see Figure 6 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] 20 34 25 tW pulse width MR, LOW; see Figure 9 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] 20 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 7 of 19 NXP Semiconductors 74LV259 8-bit addressable latch Table 8. Dynamic characteristics …continued GND = 0 V; For test circuit see Figure 12. Symbol Parameter tsu set-up time Conditions D, An to LE; see Figure 10 and Figure 11 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V th hold time D to LE; see Figure 10 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V th hold time An to LE; see Figure 11 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V CPD power dissipation capacitance CL = 50 pF; fi = 1 MHz; VI = GND to VCC [3] [4] [3] [3] −40 °C to +85 °C Min Typ[1] Max −40 °C to +125 °C Min Max Unit 24 18 14 5 5 5 5 5 5 35 12 9 7 −30 −10 −8 −6 −20 −7 −5 −4 19 - 29 21 17 5 5 5 5 5 5 - ns ns ns ns ns ns ns ns ns ns ns ns pF [1] [2] [3] [4] Typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. Typical value measured at VCC = 3.3 V. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 8 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 11. Waveforms VCC D input GND VCC LE input GND tW tPHL VOH Qn output VOL VM 001aah121 VM tPLH Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The enable input (LE) to output (Qn) propagation delays and the enable input pulse width VCC An input GND tPHL VOH Qn output VOL VM 001aah122 VM tPLH Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. The address input (An) to output (Qn) propagation delays VCC D input GND tPHL VOH Qn output VOL VM 001aah123 VM tPLH Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The data input (D) to output (Qn) propagation delays 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 9 of 19 NXP Semiconductors 74LV259 8-bit addressable latch VCC MR input GND tW tPHL VOH Qn output VOL VM 001aah124 VM Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. The conditional reset input (MR) to output (Qn) propagation delays VCC LE input GND VM tsu VCC D input GND VM tsu th th VOH Qn output VOL 001aah125 Q=D VM Q=D Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10. The data set-up and hold times for the D input to the LE input VCC An input GND VM ADDRESS STABLE tsu VCC th LE input GND VM 001aah126 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 11. The address input set-up and hold times for the An inputs to the LE input 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 10 of 19 NXP Semiconductors 74LV259 8-bit addressable latch Table 9. VCC < 2.7 V Measurement points Input VM 0.5VCC 1.5 V Output VM 0.5VCC 1.5 V Supply voltage 2.7 V to 3.6 V VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 1 kΩ VO 001aaa663 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 12. Load circuit for switching times Table 10. VCC < 2.7 V 2.7 V to 3.6 V Test data Input VI VCC 2.7 V tr, tf ≤ 2.5 ns ≤ 2.5 ns Supply voltage 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 11 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 13. Package outline SOT38-4 (DIP16) 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 12 of 19 NXP Semiconductors 74LV259 8-bit addressable latch SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 13 of 19 NXP Semiconductors 74LV259 8-bit addressable latch SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT338-1 (SSOP16) 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 14 of 19 NXP Semiconductors 74LV259 8-bit addressable latch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 16. Package outline SOT403-1 (TSSOP16) 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 15 of 19 NXP Semiconductors 74LV259 8-bit addressable latch DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT763-1 (DHVQFN16) 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 16 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 13. Abbreviations Table 11. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 12. 74LV259_3 Modifications: Revision history Release date 20080102 Data sheet status Product data sheet Change notice Supersedes 74LV259_2 Document ID • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN16 package added. Section 7: derating values added for DHVQFN16 package. Section 12: outline drawing added for DHVQFN16 package. Product specification Product specification 74LV259_1 - 74LV259_2 74LV259_1 19980520 19970606 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 17 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 18 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 January 2008 Document identifier: 74LV259_3