74LV32PW

74LV32 Quad 2-input OR gate Rev. 03 — 9 November 2007 Product data sheet 1. General description The 74LV32 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32. The 74LV32 provides a quad 2-input OR function. 2. Features s s s s s Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Multiple package options s Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74LV32N 74LV32D 74LV32DB 74LV32PW 74LV32BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name DIP14 SO14 SSOP14 TSSOP14 Description plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT27-1 SOT108-1 SOT337-1 SOT402-1 SOT762-1 Type number DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm NXP Semiconductors 74LV32 Quad 2-input OR gate 4. Functional diagram 1 2 ≥1 3 4 1 2 4 5 9 10 12 13 1A 1B 2A 2B 3A 3B 4A 4B 1Y 3 5 ≥1 6 2Y 6 9 10 ≥1 8 3Y 8 A 12 13 B 4Y 11 ≥1 11 Y mna241 mna242 mna243 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74LV32 terminal 1 index area 14 VCC 13 4B 12 4A 11 4Y VCC 7 (1) 74LV32 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 001aah104 1B 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 8 3A 3Y 2Y 1Y 2A 2B 2 3 4 5 6 GND 3Y 8 1 1A 10 3B 9 3A 001aah105 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 2 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 5.2 Pin description Table 2. Symbol 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description data input data input data output data input data input data output ground (0 V) data output data input data input data output data input data input supply voltage 6. Functional description Table 3. Function selection H = HIGH voltage level; L = LOW voltage level; X = don’t care Input nA H X L nB X H L Output nY H H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] Conditions Min −0.5 −50 −65 Max +7.0 ±20 ±50 ±25 50 +150 Unit V mA mA mA mA mA °C 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 3 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Ptot Parameter total power dissipation DIP14 package SO14 package (T)SSOP14 package DHVQFN14 package [1] [2] [3] [4] [5] Conditions Tamb = −40 °C to +125 °C [2] [3] [4] [5] Min - Max 750 500 500 500 Unit mW mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 12 mW/K above 70 °C. Ptot derates linearly with 8 mW/K above 70 °C. Ptot derates linearly with 5.5 mW/K above 60 °C. Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO Tamb ∆t/∆V Parameter supply voltage[1] input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.0 V to 2.0 V VCC = 2.0 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 5.5 V [1] Conditions Min 1.0 0 0 −40 - Typ 3.3 +25 - Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V °C ns/V ns/V ns/V ns/V The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 4 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL lO = −100 µA; VCC = 1.2 V lO = −100 µA; VCC = 2.0 V lO = −100 µA; VCC = 2.7 V lO = −100 µA; VCC = 3.0 V lO = −100 µA; VCC = 4.5 V lO = −6 mA; VCC = 3.0 V lO = −12 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.2 V IO = 100 µA; VCC = 2.0 V IO = 100 µA; VCC = 2.7 V IO = 100 µA; VCC = 3.0 V IO = 100 µA; VCC = 4.5 V IO = 6 mA; VCC = 3.0 V IO = 12 mA; VCC = 4.5 V II ICC ∆ICC CI [1] −40 °C to +85 °C Min VCC 1.4 2.0 0.7VCC 1.8 2.5 2.8 4.3 2.4 3.6 Typ[1] 0.6 0.4 1.2 2.0 2.7 3.0 4.5 2.82 4.2 0 0 0 0 0 0.25 0.35 3.5 Max GND 0.6 0.8 0.3VCC 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 - −40 °C to +125 °C Unit Min VCC 1.4 2.0 0.7VCC 1.8 2.5 2.8 4.3 2.2 3.5 Max GND 0.6 0.8 V V V V V V V 0.3VCC V 0.2 0.2 0.2 0.2 0.50 0.65 1.0 40 850 V V V V V V V V V V V V V V µA µA µA pF input leakage current supply current additional supply current input capacitance VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V Typical values are measured at Tamb = 25 °C. 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 5 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol Parameter tpd propagation delay Conditions nA, nB to nY; see Figure 6 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] [3] [3] [2] −40 °C to +85 °C Min Typ[1] 40 14 10 6.0 8.0 16 Max 22 16 13 10 - −40 °C to +125 °C Min Max 28 20 16 13 - Unit ns ns ns ns ns ns pF [1] [2] [3] [4] All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. Typical values are measured at nominal supply voltage (VCC = 3.3 V). CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 6 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 11. Waveforms VI nA, nB input GND t PHL t PLH VM nY output VM mna244 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The input (nA, nB) to output (nY) propagation delays Table 8. VCC < 2.7 V 2.7 V to 3.6 V ≥ 4.5 V Measurement points Input VM 0.5VCC 1.5 V 0.5VCC Output VM 0.5VCC 1.5 V 0.5VCC Supply voltage VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 1 kΩ VO 001aaa663 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 7. Load circuit for switching times Table 9. VCC < 2.7 V 2.7 V to 3.6 V ≥ 4.5 V Test data Input VI VCC 2.7 V VCC tr, tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Supply voltage 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 7 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D seating plane ME A2 A L A1 c Z e b1 b 14 8 MH wM (e 1) pin 1 index E 1 7 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 8. Package outline SOT27-1 (DIP14) 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 8 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT108-1 (SO14) 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 9 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE vM A Z 14 8 Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT337-1 (SSOP14) 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 10 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 11. Package outline SOT402-1 (TSSOP14) 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 11 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 12 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. 74LV32_3 Modifications: Revision history Release date 20071109 Data sheet status Product data sheet Change notice Supersedes 74LV32_2 Document ID • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN14 package added. Section 8: derating values added for DHVQFN14 package. Section 12: outline drawing added for DHVQFN14 package. Product specification Product specification 74LV32_1 - 74LV32_2 74LV32_1 19980420 19970203 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 13 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LV32_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 November 2007 14 of 15 NXP Semiconductors 74LV32 Quad 2-input OR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 November 2007 Document identifier: 74LV32_3