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74LV4052PW-Q100J

74LV4052PW-Q100J

  • 厂商:

    NXP(恩智浦)

  • 封装:

    TSSOP16

  • 描述:

    NOW NEXPERIA 74LV4052PW-Q100 - D

  • 数据手册
  • 价格&库存
74LV4052PW-Q100J 数据手册
74LV4052-Q100 Dual 4-channel analog multiplexer/demultiplexer Rev. 3 — 22 October 2015 Product data sheet 1. General description The 74LV4052-Q100 is a dual 4-channel analog multiplexer/demultiplexer with a common select logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logics include two digital select inputs (S0 and S1) and an active LOW enable input (E). With E LOW, one of the four switches is selected (low impedance ON-state) by S0 and S1. With E HIGH, all switches are in the high impedance OFF-state, independent of S0 and S1. VCC and GND are the supply voltage pins for the digital control inputs (S0, S1 and E). The VCC to GND ranges are 1.0 V to 6.0 V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Optimized for low-voltage applications: 1.0 V to 6.0 V  Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  Low ON resistance:  145  (typical) at VCC  VEE = 2.0 V  90  (typical) at VCC  VEE = 3.0 V  60  (typical) at VCC  VEE = 4.5 V  Logic level translation:  To enable 3 V logic to communicate with 3 V analog signals  Typical ‘break before make’ built in  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 74LV4052-Q100 Nexperia Dual 4-channel analog multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Type number 74LV4052D-Q100 Package Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74LV4052PW-Q100 40 C to +125 C 4. Functional diagram 9&&      6 (  /2*,& /(9(/ &219(56,21 
74LV4052PW-Q100J 价格&库存

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