74LV595PW/AUJ

74LV595 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 5 — 29 September 2021 Product data sheet 1. General description The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 1.0 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C Has a shift register with direct clear Output capability: • Parallel outputs; bus driver • Serial output; standard Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to 85 °C and -40 °C to 125 °C 3. Applications • • Serial-to-parallel data conversion Remote control holding register 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV595D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV595PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 5. Functional diagram 13 11 SHCP STCP Q7S Q0 Q1 14 Q2 Q3 DS Q4 Q5 Q6 Q7 MR 10 Fig. 1. EN3 12 12 C2 10 15 C1/ 14 1 SRG8 R 11 9 1D 2D 3 2 1 2 3 3 4 4 5 5 6 6 7 7 OE 13 15 9 mna553 mna552 Logic symbol Fig. 2. Logic symbol (IEEE/IEC) 14 DS 11 SHCP 10 MR 8-STAGE SHIFT REGISTER Q7S 12 STCP 13 OE 9 8-BIT STORAGE REGISTER 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 1 Fig. 3. 2 3 4 5 6 7 mna554 Functional diagram 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 2 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state STAGE 0 DS D STAGES 1 TO 6 Q D STAGE 7 Q D CP Q7S Q FF7 FF0 CP R R SHCP MR D Q D Q LATCH LATCH CP CP STCP OE Q0 Fig. 4. Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna555 Logic diagram SHCP DS STCP MR OE Z-state Q0 Z-state Q1 Z-state Q6 Z-state Q7 Q7S mna556 Fig. 5. Timing diagram 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 3 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 6. Pinning information 6.1. Pinning 74LV595 Q1 1 16 VCC Q2 2 15 Q0 Q3 3 14 DS Q4 4 13 OE Q5 5 12 STCP Q6 6 11 SHCP Q7 7 GND 8 74LV595 10 MR 9 Q7S Q1 1 16 VCC Q2 2 15 Q0 Q3 3 14 DS Q4 4 13 OE Q5 5 12 STCP Q6 6 11 SHCP Q7 7 10 MR GND 8 9 001aaj970 Fig. 6. Q7S mla001 Pin configuration SOT109-1 (SO16) Fig. 7. Pin configuration SOT403-1 (TSSOP16) 6.2. Pin description Table 2. Pin description Symbol Pin Description Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input VCC 16 supply voltage 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 4 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 7. Functional description Table 3. Function table H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. Input Output Function SHCP STCP OE MR DS Q7S Qn X X L L X L NC a LOW-state on MR only affects the shift register X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state ↑ X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages ↑ ↑ L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +4.6 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±50 mA IO output current -0.5 V < VO < VCC + 0.5 V - standard driver outputs 25 mA bus driver outputs ICC supply current IGND ground current Tstg storage temperature Ptot total power dissipation [1] 35 mA standard driver outputs 50 mA bus driver outputs 70 mA standard driver outputs -50 mA bus driver outputs -70 mA Tamb = -40 °C to +125 °C [1] -65 +150 °C - 500 mW For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 5 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate Min Typ Max Unit 1.0 3.3 3.6 V 0 - VCC V 0 - VCC V -40 - +125 °C VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V 10. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current 74LV595 Product data sheet Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 1.2 V - 1.2 - - - V VCC = 2.0 V 1.8 2.0 - 1.8 - V VCC = 2.7 V 2.5 2.7 - 2.5 - V VCC = 3.0 V 2.8 3.0 - 2.8 - V standard outputs; VI = VIH or VIL; IO = -6 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V bus outputs; VI = VIH or VIL; IO = -8 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V VCC = 1.2 V - 0 - - - V VCC = 2.0 V - 0 0.2 - 0.2 V VCC = 2.7 V - 0 0.2 - 0.2 V VCC = 3.0 V - 0 0.2 - 0.2 V standard driver outputs VCC = 3.0 V; IO = 6 mA - 0.25 0.4 - 0.5 V bus driver outputs VCC = 3.0 V; IO = 8 mA - 0.20 0.4 - 0.5 V VCC = 3.6 V; VI = 5.5 V or GND - - 1.0 - 1.0 μA all outputs; VI = VIH or VIL; IO = -100 μA all outputs; VI = VIH or VIL; IO = 100 μA All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 6 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 3.6 V - - 5 - 10 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - - 20 - 160 μA ΔICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V - - 500 - 850 μA CI input capacitance - 3.5 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 13. Symbol Parameter tpd propagation delay Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max VCC = 1.2 V - 95 - - - ns VCC = 2.0 V - 32 61 - 75 ns VCC = 2.7 V - 24 45 - 55 ns VCC = 3.3 V; CL = 15 pF - 15 - - - ns - 18 36 - 44 ns VCC = 1.2 V - 100 - - - ns VCC = 2.0 V - 34 65 - 77 ns VCC = 2.7 V - 25 48 - 56 ns VCC = 3.3 V; CL = 15 pF - 16 - - - ns - 19 38 - 45 ns VCC = 1.2 V - 85 - - - ns VCC = 2.0 V - 29 56 - 66 ns VCC = 2.7 V - 21 41 - 49 ns VCC = 3.3 V; CL = 15 pF - 14 - - - ns - 16 33 - 33 ns VCC = 1.2 V - 85 - - - ns VCC = 2.0 V - 29 56 - 66 ns VCC = 2.7 V - 21 41 - 49 ns - 16 33 - 39 ns VCC = 1.2 V - 65 - - - ns VCC = 2.0 V - 24 40 - 49 ns VCC = 2.7 V - 18 32 - 37 ns - 14 26 - 30 ns SHCP to Q7S; see Fig. 8 [2] VCC = 3.0 V to 3.6 V [3] STCP to Qn; see Fig. 9 [2] VCC = 3.0 V to 3.6 V [3] MR to Q7S; see Fig. 11 VCC = 3.0 V to 3.6 V ten enable time OE to Qn; see Fig. 12 VCC = 3.0 V to 3.6 V tdis disable time OE to Qn; see Fig. 12 VCC = 3.0 V to 3.6 V 74LV595 Product data sheet [3] [4] [3] [5] [3] All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 7 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter tW pulse width Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max VCC = 2.0 V 34 10 - 41 - ns VCC = 2.7 V 25 8 - 30 - ns 20 6 - 24 - ns 34 7 - 41 - ns 25 5 - 30 - ns 20 4 - 24 - ns VCC = 2.0 V 34 10 - 41 - ns VCC = 2.7 V 25 8 - 30 - ns 20 6 - 24 - ns VCC = 1.2 V - 40 - - - ns VCC = 2.0 V 26 14 - 31 - ns VCC = 2.7 V 19 10 - 23 - ns 15 8 - 18 - ns VCC = 1.2 V - 40 - - - ns VCC = 2.0 V 26 14 - 31 - ns VCC = 2.7 V 19 10 - 23 - ns 15 8 - 18 - ns VCC = 1.2 V - -10.0 - - - ns VCC = 2.0 V 5.0 -4.0 - 5.0 - ns VCC = 2.7 V 5.0 -3.0 - 5.0 - ns 5.0 -2.0 - 5.0 - ns VCC = 1.2 V - -35 - - - ns VCC = 2.0 V 5.0 -12.0 - 5.0 - ns VCC = 2.7 V 5.0 -9.0 - 5.0 - ns 5.0 -7.0 - 5.0 - ns VCC = 2.0 V 14.0 40.0 - 12 - MHz VCC = 2.7 V 19.0 58.0 - 16 - MHz - 77 - - - MHz 24.0 70.0 - 20 - MHz SHCP, HIGH or LOW; see Fig. 8 VCC = 3.0 V to 3.6 V [3] STCP, HIGH or LOW; see Fig. 9 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] MR LOW; see Fig. 11 VCC = 3.0 V to 3.6 V tsu set-up time [3] DS to SHCP; see Fig. 10 VCC = 3.0 V to 3.6 V [3] SHCP to STCP; see Fig. 9 VCC = 3.0 V to 3.6 V th hold time VCC = 3.0 V to 3.6 V trec recovery time [3] MR to SHCP; see Fig. 11 VCC = 3.0 V to 3.6 V fmax [3] DS to SHCP; see Fig. 10 [3] maximum frequency SHCP or STCP; see Fig. 8 and Fig. 9 VCC = 3.3 V; CL = 15 pF VCC = 3.0 V to 3.6 V 74LV595 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 8 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter CPD [1] [2] [3] [4] [5] [6] Conditions power dissipation capacitance -40 °C to +85 °C VI = GND to VCC; VCC = 3.0 V [6] -40 °C to +125 °C Unit Min Typ [1] Max Min Max - 115 - - - pF Typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. Typical value measured at VCC = 3.3 V. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 11.1. Waveforms and test circuit 1/fmax VI SHCP input VM GND tW t PHL t PLH VOH VM Q7S output VOL mna557 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig. 8. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency VI SHCP input VM GND 1/fmax t su VI STCP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna558 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig. 9. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 9 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI VM SHCP input GND t su t su th th VI VM DS input GND VOH VM Q7S output VOL mna560 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load. Fig. 10. The data set-up and hold times for the serial data input (DS) VI VM MR input GND tW t rec VI SHCP input VM GND t PHL VOH VM Q7S output VOL mna561 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig. 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 10 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI VM OE input GND tPLZ output LOW-to-OFF OFF-to-LOW VCC VM VX VOL VOH output HIGH-to-OFF OFF-to-HIGH tPZL tPHZ tPZH VY VM GND outputs enabled outputs disabled outputs enabled 001aae821 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig. 12. Enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY VCC < 2.7 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH - 0.1VCC VCC ≥ 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 11 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 13. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH < 2.7 V VCC ≤ 2.5 ns 50 pF 1 kΩ open 2VCC GND 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 1 kΩ open 2VCC GND 74LV595 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 12 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 14. Package outline SOT109-1 (SO16) 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 13 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 15. Package outline SOT403-1 (TSSOP16) 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 14 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV595 v.5 20210929 Product data sheet - Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LV595DB (SOT338-1/SSOP16) removed. Section 1 and Section 2 updated. Section 8: Derating values for Ptot total power dissipation updated. 74LV595 v.4 20160318 Modifications: • 74LV595 v.3 20090421 Modifications: • • 74LV595 v.4 Product data sheet - 74LV595 v.3 Type number 74LV595N (SOT38-4) removed. Product data sheet - 74LV595 v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 74LV595 v.2 980402 Product data sheet - 74LV595 v.1 74LV595 v.1 970606 Product data sheet - - 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 15 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state 15. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 16 / 17 74LV595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................2 5. Functional diagram.......................................................2 6. Pinning information......................................................4 6.1. Pinning.........................................................................4 6.2. Pin description............................................................. 4 7. Functional description................................................. 5 8. Limiting values............................................................. 5 9. Recommended operating conditions..........................6 10. Static characteristics..................................................6 11. Dynamic characteristics.............................................7 11.1. Waveforms and test circuit........................................ 9 12. Package outline........................................................ 13 13. Abbreviations............................................................ 15 14. Revision history........................................................15 15. Legal information......................................................16 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 29 September 2021 74LV595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 September 2021 © Nexperia B.V. 2021. All rights reserved 17 / 17