74LVC16244ABQ

74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Rev. 09 — 18 March 2010 Product data sheet 1. General description The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with 3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels High-impedance when VCC = 0 V All data inputs have bus hold. (74LVCH16244A only) Complies with JEDEC standard JESD8-B / JESD36 ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 3. Ordering information Table 1. Ordering information Temperature range −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Package Name 74LVC16244ADL 74LVCH16244ADL 74LVC16244ADGG 74LVCH16244ADGG 74LVC16244AEV 74LVCH16244AEV 74LVC16244ABQ 74LVCH16244ABQ VFBGA56 TSSOP48 SSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm plastic thin shrink small outline package; 48 leads; body width 6.1 mm Version SOT370-1 SOT362-1 Type number plastic very thin fine-pitch ball grid array package; SOT702-1 56 balls; body 4.5 × 7 × 0.65 mm HXQFN60U plastic thermal enhanced extremely thin quad flat SOT1134-1 package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm 4. Functional diagram 1 1OE 48 2OE 25 3OE 24 4OE 1A0 1A1 17 1A2 1A3 1 1OE 25 2Y0 3OE 2A0 2A1 41 40 2A0 8 9 30 29 4A0 4Y0 19 20 2A2 2A3 2A1 2Y1 4A1 4Y1 3A0 3A1 38 2A2 2Y2 11 27 4A2 4Y2 22 3A2 3A3 4A0 23 4A1 4A2 4A3 001aae506 47 46 1A0 1Y0 2 3 36 35 3A0 3Y0 13 14 1A1 1Y1 3A1 3Y1 EN1 EN2 EN3 EN4 1 1 2 3 5 6 1 2 8 9 11 12 1 3 13 14 16 17 1 4 19 20 22 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 44 1A2 1Y2 5 33 3A2 3Y2 16 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 43 1A3 1Y3 6 32 3A3 3Y3 37 2A3 2OE 2Y3 12 26 4A3 4OE 4Y3 48 24 001aae231 Pin numbers are shown for SSOP48 and TSSOP48 packages only. Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 2 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state VCC data input to internal circuit mna705 Fig 3. Bus hold circuit 5. Pinning information 5.1 Pinning 1OE 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y0 2Y1 1 2 3 4 5 6 7 8 9 48 2OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 2A0 40 2A1 39 GND 38 2A2 37 2A3 36 3A0 35 3A1 34 GND 33 3A2 32 3A3 31 VCC 30 4A0 29 4A1 28 GND 27 4A2 26 4A3 25 3OE 001aaj052 GND 10 2Y2 11 2Y3 12 3Y0 13 3Y1 14 GND 15 3Y2 16 3Y3 17 VCC 18 4Y0 19 4Y1 20 GND 21 4Y2 22 4Y3 23 4OE 24 74LVC16244A 74LVCH16244A ball A1 74LVCH16244A index area 123456 A B C D E F G H J K 001aaj053 74LVC16244A Transparent top view Fig 4. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) Fig 5. Pin configuration SOT702-1 (VFBGA56) 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 3 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state terminal 1 index area D1 A32 A31 A30 A29 A28 A27 D4 A1 D5 B20 B19 B18 D8 A26 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 GND(1) B11 B12 B15 B16 B17 A25 A24 A23 A22 74LVC16244A 74LVCH16244A B14 A21 B13 A20 A19 A18 A10 D6 B8 B9 B10 D7 A17 D2 A11 A12 A13 A14 A15 A16 D3 001aaj054 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration SOT1134-1 (HXQFN60U) 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 4 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 5.2 Pin description Table 2. Symbol Pin description Pin SOT370-1 and SOT362-1 1OE, 2OE, 3OE, 4OE 1, 48, 25, 24 SOT702-1 A1, A6, K6, K1 B2, B1, C2, C1 D2, D1, E2, E1 F1, F2, G1, G2 H1, H2, J1, J2 B3, B4, D3, D4, G3, G4, J3, J4 C3, C4, H3, H4 B5, B6, C5, C6 D5, D6, E5, E6 F6, F5, G6, G5 H6, H5, J6, J5 A2, A3, A4, A5, K2, K3, K4, K5 SOT1134-1 A30, A29, A14, A13 B20, A31, D5, D1 A2, B2, B3, A5 A6, B5, B6, A9 D2, D6, A12, B8 A32, A3, A8, A11, A16, A19, A24, A27 A1, A10, A17, A26 B18, A28, D8, D4 A25, B16, B15, A22 A21, B13, B12, A18 D3, D7, A15, B10 A4, A7, A20, A23, B1, B4, B7, B9, B11, B14, B17, B19 output enable input (active LOW) data output data output data output data output ground (0 V) supply voltage data input data input data input data input not connected Description 1Y0 to 1Y3 2, 3, 5, 6 2Y0 to 2Y3 8, 9, 11, 12 3Y0 to 3Y3 13, 14, 16, 17 4Y0 to 4Y3 19, 20, 22, 23 GND VCC 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 1A0 to 1A3 47, 46, 44, 43 2A0 to 2A3 41, 40, 38, 37 3A0 to 3A3 36, 35, 33, 32 4A0 to 4A3 30, 29, 27, 26 n.c. - 6. Functional description Table 3. Control nOE L L H [1] Function table[1] Input nAn L H X Output nYn L H Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 5 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C; (T)SSOP48 package VFBGA56 package HXQFN60U package [1] [2] [3] [4] [3] [4] [4] Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [2] [2] Max +6.5 +6.5 ±50 VCC + 0.5 +6.5 ±50 100 +150 500 1000 1000 Unit V mA V mA V V mA mA mA °C mW mW mW VO > VCC or VO < 0 V output HIGH or LOW output 3-state VO = 0 V to VCC −0.5 −0.5 −100 −65 - The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC Recommended operating conditions Parameter supply voltage Conditions maximum speed performance functional VI VO Tamb Δt/ΔV input voltage output voltage ambient temperature input transition rise and fall rate output HIGH or LOW output 3-state in free air VCC = 1.2 V to 2.7 V VCC = 2.7 V to 3.6 V Min 2.7 1.2 0 0 0 −40 0 0 Typ Max 3.6 3.6 5.5 VCC 5.5 +125 20 10 Unit V V V V V °C ns/V ns/V 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 6 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage Conditions VCC = 1.2 V VCC = 2.7 V to 3.6 V VCC = 1.2 V VCC = 2.7 V to 3.6 V −40 °C to +85 °C Min VCC 2.0 VCC − 0.2 2.2 2.4 2.2 [2] −40 °C to +125 °C Unit Min VCC 2.0 VCC − 0.3 2.05 2.25 2.0 Max 0 0.8 0.3 0.6 0.8 ±20 ±20 V V V V V V V V V V V μA μA 0 Typ[1] VCC 0 ±0.1 ±0.1 Max 0.8 0.20 0.40 0.55 ±5 ±5 HIGH-level output VI = VIH or VIL voltage IO = −100 μA; VCC = 2.7 V to 3.6 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output VI = VIH or VIL voltage IO = 100 μA; VCC = 2.7 V to 3.6 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II IOZ input leakage current OFF-state output current VI = 5.5 V or GND; VCC = 3.6 V VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - [2][3] IOFF ICC ΔICC CI IBHL IBHH IBHLO power-off leakage VI or VO = 5.5 V; VCC = 0.0 V current supply current additional supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V per input pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V [4][5] ±0.1 0.1 5 5.0 - ±10 20 500 - 60 −60 500 ±20 80 5000 - μA μA μA pF μA μA μA input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC bus hold LOW current bus hold HIGH current bus hold LOW overdrive current VCC = 3.0 V; VI = 0.8 V VCC = 3.0 V; VI = 2.0 V VCC = 3.6 V 75 −75 500 [4][5] [4][6] 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 7 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHHO bus hold HIGH overdrive current Conditions VCC = 3.6 V [4][6] −40 °C to +85 °C Min −500 Typ[1] Max - −40 °C to +125 °C Unit Min −500 Max μA [1] [2] [3] [4] [5] [6] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. For I/O ports the parameter IOZ includes the input leakage current. Valid for data inputs of bus hold parts only (74LVCH16244A). Note that control inputs do not have a bus hold circuit. The specified sustaining current at the data input holds the input below the specified VI level. The specified overdrive current at the data input forces the data input to the opposite input state. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tpd propagation delay Conditions nAn to nYn; see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V ten enable time nOE to nYn; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tdis disable time nOE to nYn; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [2] [2] [1] [2] [1] [1] −40 °C to +85 °C Min 1.0 1.1 1.0 1.0 1.0 1.8 Typ 11.0 3.0 15.0 3.5 10.0 3.7 Max 4.7 4.1 5.8 4.6 6.2 5.2 −40 °C to +125 °C Unit Min 1.0 1.1 1.0 1.0 1.0 1.8 Max 6.0 5.5 7.5 6.0 8.0 6.5 ns ns ns ns ns ns ns ns ns 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 8 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter CPD power dissipation capacitance Conditions per buffer; VI = GND to VCC; VCC = 3.3 V outputs enabled outputs disabled [3] −40 °C to +85 °C Min Typ 12 4.0 Max - −40 °C to +125 °C Unit Min Max pF pF [1] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [2] [3] Typical values are measured at Tamb = 25 °C and VCC = 3.3 V. CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. 11. Waveforms VI nAn input GND tPLH VOH nYn output VOL VM VM mna171 VM VM tPHL Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The input (nAn) to output (nYn) propagation delays 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 9 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM outputs disabled outputs enabled mna362 Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 8. VCC 1.2 V 2.7 V 3-state enable and disable times. Measurement points Input VI VCC 2.7 V 2.7 V VM 0.5 × VCC 1.5 V 1.5 V Output VM 0.5 × VCC 1.5 V 1.5 V VX VOL + 0.1 V VOL + 0.3 V VOL + 0.3 V VY VOH − 0.1 V VOH − 0.3 V VOH − 0.3 V Supply voltage 3.0 V to 3.6 V 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 10 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 9. Load circuit for measuring switching times Test data Input VI tr, tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VCC 2.7 V 2.7 V Load CL 50 pF 50 pF 50 pF RL 500 Ω[1] 500 Ω 500 Ω VEXT tPLH, tPHL open open open tPLZ, tPZL 2 × VCC 2 × VCC 2 × VCC tPHZ, tPZH GND GND GND Supply voltage 1.2 V 2.7 V 3.0 V to 3.6 V [1] The circuit performs better when RL = 1 kΩ. 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 11 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE vM A Z 48 25 Q A2 A1 (A 3) θ Lp 1 24 A pin 1 index L wM detail X e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT370-1 (SSOP48) 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 12 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c y HE vMA Z 48 25 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp 24 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT362-1 (TSSOP48) 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 13 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm SOT702-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 b e CAB ∅w M C ∅v M C y1 C y K J H e G F E D C B A ball A1 index area 1 2 3 4 5 6 1/2 e2 e X DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.3 0.2 A2 0.7 0.6 b 0.45 0.35 D 4.6 4.4 E 7.1 6.9 e 0.65 e1 3.25 e2 5.85 v 0.15 w 0.08 y 0.08 y1 0.1 0 2.5 scale 5 mm OUTLINE VERSION SOT702-1 REFERENCES IEC JEDEC MO-225 JEITA EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 Fig 12. Package outline SOT702-1 (VFBGA56) 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 14 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm D B A SOT1134-1 terminal 1 index area E A A1 detail X e2 e1 1/2 e v w L1 CAB C D2 D6 A10 eR B7 e b A11 B8 B10 A16 D7 A17 B11 D3 v w CAB C y1 C C y L e Eh 1/2 e B1 A1 terminal 1 index area D5 D1 B20 A32 Dh k 0 Dimensions Unit mm A A1 b D 4.1 4.0 3.9 Dh 1.90 1.85 1.80 E 6.1 6.0 5.9 Eh 3.90 3.85 3.80 e 0.5 e1 1 2.5 scale e2 2.5 B18 A27 D8 D4 B17 A26 e3 e4 X 5 mm e3 3 e4 4.5 eR 0.5 k L L1 0.125 0.075 0.025 v w y y1 0.1 sot1134-1_po max 0.50 0.05 0.35 nom 0.48 0.02 0.30 min 0.46 0.00 0.25 0.25 0.35 0.20 0.30 0.15 0.25 0.07 0.05 0.08 Outline version SOT1134-1 References IEC --JEDEC --JEITA --- European projection Issue date 08-12-17 09-01-22 Fig 13. Package outline SOT1134-1 (HXQFN60U) 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 15 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20100318 Data sheet status Product data sheet Change notice Supersedes 74LVC_LVCH16244A_8 Document ID 74LVC_LVCH16244A_9 Modifications: 74LVC_LVCH16244A_8 74LVC_LVCH16244A_7 74LVC_LVCH16244A_6 74LVC_LVCH16244A_5 74LVC_H16244A_4 74LVC16244A_ 74LVCH16244A_3 74LVC16244A_2 74LVC16244A_1 • 74LVC16244ABQ and 74LVCH16244ABQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. Product data sheet Product specification Product specification Product specification Product specification Product specification Product specification 74LVC_LVCH16244A_7 74LVC_LVCH16244A_6 74LVC_LVCH16244A_5 74LVC_H16244A_4 74LVC16244A_ 74LVCH16244A_3 74LVC16244A_2 74LVC16244A_1 - 20081117 20031208 20030130 20021030 19971028 19971028 19970630 - 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 16 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVC_LVCH16244A_9 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 17 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC_LVCH16244A_9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 09 — 18 March 2010 18 of 19 NXP Semiconductors 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 March 2010 Document identifier: 74LVC_LVCH16244A_9