74LVC169D,112

74LVC169 Presettable synchronous 4-bit up/down binary counter Rev. 6 — 29 November 2012 Product data sheet 1. General description The 74LVC169 is a synchronous presettable 4-bit binary counter which features an internal look-ahead carry circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the LOW-to-HIGH transition of the clock. The counter is fully programmable; that is, the outputs may be preset to any number between 0 and its maximum count. Presetting is synchronous with the clock and takes place regardless of the levels of the count enable inputs. A LOW level on the parallel enable (pin PE) input disables the counter and causes the data at the Dn input to be loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the counter counts up, when LOW, it counts down. The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a LOW-level output pulse with a duration approximately equal to a HIGH level portion of pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded stages. The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing the control of data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a set-up time before the next LOW-to-HIGH transition of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters the flip-flops on the next LOW-to-HIGH transition of the clock. 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be HIGH. The pin U/D input determines the direction of the counting. The terminal count output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW, when a counter reaches 15 in the count up mode. The pin TC output state is not a function of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For this reason the use of pin TC as a clock signal is not recommended; see the following logic equations: count enable = CEP  CET  PE count up: TC = Q3  Q2  Q1  Q0  CET  U  D count down: TC = Q3  Q2  Q1  Q0  CET  U  D 2. Features and benefits          5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Up/down counting Two count enable inputs for n-bit cascading Built-in look-ahead carry capability Presettable for programmable operation Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2.7 V)  JESD8-C/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 2 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 3. Ordering information Table 1. Ordering information Type number Temperature range Package Name Description Version 74LVC169D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LVC169DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74LVC169PW 40 C to +125 C 74LVC169BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1 quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm 4. Functional diagram CTR4 M1 [LOAD] 9 M2 [COUNT] 3 4 5 6 M3 [UP] 1 D0 9 PE 1 U/D 2 CP 7 CEP 10 CET Q0 D1 D2 D3 M4 [DOWN] 10 7 G5 3, 5 CT=15 G6 4, 5 CT=0 2, 3, 5, 6+/C7 TC 2 15 2, 3, 5, 6− 3 Q1 Q2 1,7D 4 Q3 5 14 13 12 6 11 Logic symbol 74LVC169 Product data sheet 14 [1] 13 [2] 12 [4] 11 [8] 001aaa646 001aaa645 Fig 1. 15 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 3 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter D0 D1 D2 D3 PE 3 4 5 6 D Q CP Q D Q CP Q D Q CP Q D Q CP Q 14 13 12 11 Q0 Q1 Q2 Q3 9 CEP 7 10 CET CP U/D 2 1 15 TC 001aaa649 Fig 3. Logic diagram 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 4 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 5. Pinning information 5.1 Pinning 1 terminal 1 index area CP 2 15 TC U/D 1 16 VCC D0 3 14 Q0 CP 2 15 TC D1 4 13 Q1 D0 3 14 Q0 D2 5 D1 4 13 Q1 D3 6 D2 5 12 Q2 CEP 7 D3 6 11 Q3 8 9 CEP 7 10 CET GND 8 9 GND PE 74LVC169 16 VCC U/D 74LVC169 PE 12 Q2 GND(1) 11 Q3 10 CET 001aaa682 Transparent top view 001aaa644 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO16 and (T)SSOP16 Fig 5. Pin configuration for DHVQFN16 5.2 Pin description Table 2. Pin description Symbol Pin Description U/D 1 up/down control input CP 2 clock input (LOW-to-HIGH, edge-triggered) D0 to D3 3, 4, 5, 6 data input CEP 7 count enable input (active LOW) GND 8 ground (0 V) PE 9 parallel enable input (active LOW) CET 10 count enable carry input (active LOW) Q0 to Q3 14, 13, 12, 11 flip-flop output TC 15 terminal count output (active LOW) VCC 16 supply voltage 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 5 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 6. Functional description Table 3. Function table[1] Operating mode Parallel load (Dn to Qn) Input Output CP U/D CEP CET PE Dn Qn TC  X X X I I L *  X X X l h H * Count up (increment)  h I I h X count up * Count down (decrement)  I I I h X count down * Hold (do nothing)  X h X h X qn *  X X X h X qn H [1] H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition qn = Lower case letters indicate state of referenced output prior to the LOW-to-HIGH clock transition X = don’t care  = LOW-to-HIGH clock transition * = The TC is LOW when CET is LOW and the counter is at terminal count Terminal count up is (HHHH) and terminal count down is (LLLL) 0 1 3 4 15 5 14 6 13 7 12 11 count down count up Fig 6. 2 10 9 8 001aaa647 State diagram 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 6 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter PE D0 D1 D2 D3 CP U/D CEP and CET Q0 Q1 Q2 Q3 TC 13 14 load 15 0 count up 1 2 2 2 inhibit 1 0 15 14 13 count down 001aaa648 The following sequence is illustrated: - Load (preset) to thirteen. - Count up to fourteen, fifteen (maximum), zero, one and two. - Inhibit. - Count down to one, zero (minimum), fifteen, fourteen and thirteen. Fig 7. Typical timing sequence 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 7 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage Conditions VI < 0 V [1] VO > VCC or VO < 0 V [2] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +5.5 V - 50 mA 0.5 VCC + 0.5 V IO output current - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW Tamb = 40 C to +125 C total power dissipation Ptot [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions functional VI input voltage Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 8 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min HIGH-level VCC = 1.2 V input voltage V = 1.65 V to 1.95 V CC VIH VOH HIGH-level output voltage LOW-level output voltage Max Min Unit Max 1.08 - - 1.08 - V - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - - 0.12 - 0.12 V - - 0.35  VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC  0.2 - - VCC  0.3 - V 1.2 - - 1.05 - V 0.35  VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V IO = 4 mA; VCC = 1.65 V VOL 40 C to +125 C 0.65  VCC LOW-level VCC = 1.2 V input voltage V = 1.65 V to 1.95 V CC VIL Typ[1] IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V II input leakage current VCC = 3.6 V; VI = 5.5 V or GND - 0.1 5 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 9 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions Min Max Min Max - 17 - - - ns VCC = 1.65 V to 1.95 V 1.5 7.1 13.1 1.5 15.1 ns VCC = 2.3 V to 2.7 V 2.4 4.1 7.4 2.4 8.6 ns VCC = 2.7 V 1.5 3.9 7.2 1.5 9.0 ns VCC = 3.0 V to 3.6 V 1.5 3.7 6.6 1.5 10.0 ns - 21 - - - ns CP to Qn; see Figure 8 [2] VCC = 1.2 V CP to TC; see Figure 8 [2] VCC = 1.2 V VCC = 1.65 V to 1.95 V 2.0 8.5 14.9 2.0 17.2 ns VCC = 2.3 V to 2.7 V 3.0 4.9 8.4 3.0 9.7 ns VCC = 2.7 V 1.5 4.7 8.8 1.5 11.0 ns 1.5 4.4 7.5 1.5 9.5 ns - 19 - - - ns VCC = 1.65 V to 1.95 V 1.5 6.6 12.3 1.5 14.2 ns VCC = 2.3 V to 2.7 V 2.2 3.8 7.0 2.2 8.1 ns VCC = 2.7 V 1.5 4.0 7.2 1.5 9.0 ns VCC = 3.0 V to 3.6 V 1.5 3.4 6.2 1.5 8.0 ns - 21 - - - ns VCC = 3.0 V to 3.6 V CET to TC; see Figure 9 [2] VCC = 1.2 V U/D to TC; see Figure 10 VCC = 1.2 V tW pulse width 74LVC169 Product data sheet 40 C to +125 C Unit Typ[1] [2] VCC = 1.65 V to 1.95 V 1.0 7.3 13.7 1.0 15.8 ns VCC = 2.3 V to 2.7 V 1.7 4.2 7.7 1.7 8.9 ns VCC = 2.7 V 1.5 4.4 8.2 1.5 10.5 ns VCC = 3.0 V to 3.6 V 1.5 3.8 6.9 1.5 9.0 ns VCC = 1.65 V to 1.95 V 6.0 - - 6.0 - ns VCC = 2.3 V to 2.7 V 5.0 - - 5.0 - ns VCC = 2.7 V 5.0 - - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns CP HIGH or LOW; see Figure 8 All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 10 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter 40 C to +85 C Conditions Min tsu set-up time Typ[1] Max 40 C to +125 C Unit Min Max Dn to CP; see Figure 11 VCC = 1.65 V to 1.95 V 5.5 - - 5.5 - ns VCC = 2.3 V to 2.7 V 4.5 - - 4.5 - ns VCC = 2.7 V 3.0 - - 3.0 - ns VCC = 3.0 V to 3.6 V 2.5 1.0 - 2.5 - ns VCC = 1.65 V to 1.95 V 4.5 - - 4.5 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.5 - - 3.5 - ns VCC = 3.0 V to 3.6 V 3.0 1.2 - 3.0 - ns VCC = 1.65 V to 1.95 V 9.0 - - 9.0 - ns VCC = 2.3 V to 2.7 V 7.0 - - 7.0 - ns PE to CP; see Figure 11 U/D to CP; see Figure 12 VCC = 2.7 V 6.5 - - 6.5 - ns VCC = 3.0 V to 3.6 V 5.5 2.8 - 5.5 - ns VCC = 1.65 V to 1.95 V 9.0 - - 9.0 - ns VCC = 2.3 V to 2.7 V 6.0 - - 6.0 - ns VCC = 2.7 V 5.5 - - 5.5 - ns VCC = 3.0 V to 3.6 V 4.5 2.1 - 4.5 - ns VCC = 1.65 V to 1.95 V 1.0 - - 1.0 - ns VCC = 2.3 V to 2.7 V 1.0 - - 1.0 - ns VCC = 2.7 V 0.0 - - 0.0 - ns VCC = 3.0 V to 3.6 V 0.5 0.0 - 0.5 - ns VCC = 1.65 V to 1.95 V 100 - - 80 - MHz VCC = 2.3 V to 2.7 V 125 - - 100 - MHz CEP, CET to CP; see Figure 12 th fmax tsk(o) hold time maximum frequency output skew time 74LVC169 Product data sheet Dn, PE, CEP, CET, U/D to CP; see Figure 11 and 12 see Figure 8 VCC = 2.7 V 150 - - 120 - MHz VCC = 3.0 V to 3.6 V 150 200 - 120 - MHz - - 1.0 - 1.5 VCC = 3.0 V to 3.6 V [3] All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 ns © NXP B.V. 2012. All rights reserved. 11 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter CPD [1] power dissipation capacitance 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] VCC = 1.65 V to 1.95 V - 12.7 - - - pF VCC = 2.3 V to 2.7 V - 16.4 - - - pF VCC = 3.0 V to 3.6 V - 19.7 - - - pF per input pin; VI = GND to VCC Max Min Max [4] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volt N = number of inputs switching (CL  VCC2  fo) = sum of outputs 11. Waveforms 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Qn, TC output VOL 001aaa651 Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 8. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 12 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter VI VM CET GND tPHL tPLH VOH VI VM TC VOL 001aaa652 Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 9. Input (CET) to output (TC) propagation delays VI VM U/D GND tPHL tPLH VOH VI VM TC VOL 001aaa653 Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 10. The up/down control input (U/D) to output (TC) propagation delays 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 13 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter VI VM PE input GND t su t su th th VI VM CP input GND t su t su th th VI VM Dn input GND 001aaa654 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE) VI VM CEP, CET, U/D input GND th th tsu tsu VI VM CP input GND 001aaa655 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 12. Set-up and hold times for count enable inputs (CEP and CET) and control input (U/D) Table 8. Measurement points Supply voltage Input VCC VI VM VM 1.2 V VCC 0.5  VCC 0.5  VCC 1.65 V to 1.95 V VCC 0.5  VCC 0.5  VCC 2.3 V to 2.7 V VCC 0.5  VCC 0.5  VCC 2.7 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V 74LVC169 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 14 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf VCC  2 ns 1.65 V to 1.95 V VCC  2 ns 2.3 V to 2.7 V VCC 2.7 V 2.7 V 3.0 V to 3.6 V 2.7 V 1.2 V [1] Load CL S1 position RL tPLH, tPHL 1 k[1] open 30 pF 1 k[1] open  2 ns 30 pF 500  open  2.5 ns 50 pF 500  open  2.5 ns 50 pF 500  open 30 pF The circuit performs better when RL = 1000 k. 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 15 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 12. Application information CP U/D PE D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 PE PE PE PE U/D U/D U/D U/D CP CP CP CEP TC CET Q0 Q1 Q2 Q3 CEP TC CET Q0 Q1 Q2 Q3 CEP CP TC CET Q0 Q1 Q2 Q3 least significant 4-bit counter TC CEP CET Q0 Q1 Q2 Q3 most significant 4-bit counter 001aaa650 Fig 14. Synchronous multistage counting scheme 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 16 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT109-1 (SO16) 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 17 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT338-1 (SSOP16) 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 18 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 17. Package outline SOT403-1 (TSSOP16) 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 19 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 18. Package outline SOT763-1 (DHVQFN16) 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 20 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC169 v.6 20121129 Product data sheet - 74LVC169 v.5 Modifications: 74LVC169 v.5 • Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 20090608 Product data sheet - 74LVC169 v.4 74LVC169 v.4 20041014 Product specification - 74LVC169 v.3 74LVC169 v.3 20040512 Product specification - 74LVC169 v.2 74LVC169 v.2 19980520 Product specification - 74LVC169 v.1 74LVC169 v.1 19960823 Product specification - - 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 21 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC169 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 22 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 29 November 2012 © NXP B.V. 2012. All rights reserved. 23 of 24 74LVC169 NXP Semiconductors Presettable synchronous 4-bit up/down binary counter 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information. . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 November 2012 Document identifier: 74LVC169