74LVC1G11GW,125

74LVC1G11 Single 3-input AND gate Rev. 11 — 21 September 2021 Product data sheet 1. General description The 74LVC1G11 is a single 3-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power dissipation Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C 74LVC1G11 Nexperia Single 3-input AND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G11GW -40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC1G11GV -40 °C to +125 °C SC-74; TSOP6 plastic surface-mounted package; 6 leads SOT457 74LVC1G11GM -40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74LVC1G11GN -40 °C to +125 °C XSON6 extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9 × 1.0 × 0.35 mm 74LVC1G11GS -40 °C to +125 °C XSON6 extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0 × 1.0 × 0.35 mm 74LVC1G11GX -40 °C to +125 °C X2SON6 plastic thermal extremely thin small outline package; no leads; 6 terminals; body 1 × 0.8 × 0.35 mm SOT1255 4. Marking Table 2. Marking Type number Marking code[1] 74LVC1G11GW VU 74LVC1G11GV V11 74LVC1G11GM VU 74LVC1G11GN VU 74LVC1G11GS VU 74LVC1G11GX VU [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A 1 3 6 1 A B Y C 3 4 Logic symbol 74LVC1G11 Product data sheet 4 B Y 6 001aac033 Fig. 1. & 001aac029 Fig. 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 C Fig. 3. 001aac030 Logic diagram © Nexperia B.V. 2021. All rights reserved 2 / 16 74LVC1G11 Nexperia Single 3-input AND gate 6. Pinning information 6.1. Pinning 74LVC1G11 74LVC1G11 A 1 6 C GND 2 5 VCC B 3 4 Y A 1 6 C GND 2 5 VCC B 3 4 Y 001aac849 001aac032 Fig. 4. Pin configuration SOT363 (SC-88) and SOT457 (SC-74; TSOP6) Transparent top view Fig. 5. Pin configuration SOT886 (XSON6) 74LVC1G11 74LVC1G11 A 1 A 1 6 C GND 2 5 VCC B 3 4 Y GND 2 Transparent top view VCC 5 3 B 001aaf200 Fig. 6. C 6 4 Y aaa-019825 Transparent top view Pin configuration SOT1115 and SOT1202 (XSON6) Fig. 7. Pin configuration SOT1255 (X2SON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description A 1 data input GND 2 ground (0 V) B 3 data input Y 4 data output VCC 5 supply voltage C 6 data input 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Output Input A B C Y H H H H L X X L X L X L X X L L 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 3 / 16 74LVC1G11 Nexperia Single 3-input AND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage Active mode [1] -0.5 Power-down mode; VCC = 0 V [1] -0.5 +6.5 V - ±50 mA VI < 0 V [1] VCC + 0.5 V IO output current ICC supply current - 100 mA IGND ground current -100 - mA Ptot total power dissipation - 250 mW Tstg storage temperature -65 +150 °C [1] [2] VO = 0 V to VCC mA Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT363 (SC-88) package: Ptot derates linearly with 3.7 mW/K above 83 °C. For SOT457 (SC-74; TSOP6) package: Ptot derates linearly with 4.1 mW/K above 89 °C. For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT1115 (XSON6) package: Ptot derates linearly with 3.2 mW/K above 71 °C. For SOT1202 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT1255 (X2SON6) package: Ptot derates linearly with 3.3 mW/K above 75 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 1.65 - 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature Δt/ΔV input transition rise and fall rate Active mode Power-down mode; VCC = 0 V 74LVC1G11 Product data sheet 0 - 5.5 V -40 - +125 °C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 4 / 16 74LVC1G11 Nexperia Single 3-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage VIL LOW-level input voltage VOH Conditions -40 °C to +85 °C Unit Min Typ[1] Max Min Max 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V VCC - 0.1 - - VCC - 0.1 - V IO = -4 mA; VCC = 1.65 V 1.2 1.54 - 0.95 - V IO = -8 mA; VCC = 2.3 V 1.9 2.15 - 1.7 - V IO = -12 mA; VCC = 2.7 V 2.2 2.50 - 1.9 - V IO = -24 mA; VCC = 3.0 V 2.3 2.62 - 2.0 - V IO = -32 mA; VCC = 4.5 V 3.8 4.11 - 3.4 - V - - 0.10 - 0.10 V IO = 4 mA; VCC = 1.65 V - 0.07 0.45 - 0.70 V IO = 8 mA; VCC = 2.3 V - 0.12 0.30 - 0.45 V IO = 12 mA; VCC = 2.7 V - 0.17 0.40 - 0.60 V IO = 24 mA; VCC = 3.0 V - 0.33 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - 0.39 0.55 - 0.80 V VCC = 1.65 V to 1.95 V VI = VIH or VIL HIGH-level output voltage IO = -100 μA; VCC = 1.65 V to 5.5 V VI = VIH or VIL LOW-level output voltage IO = 100 μA; VCC = 1.65 V to 5.5 V VOL -40 °C to +125 °C II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±1 - ±1 μA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±2 - ±2 μA ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 4 - 4 μA ΔICC additional VI = VCC - 0.6 V; IO = 0 A; supply current VCC = 2.3 V to 5.5 V; per pin - 5 500 - 500 μA CI input capacitance - 4 - - - pF [1] VCC = 3.3 V; VI = GND to VCC All typical values are measured at Tamb = 25 °C. 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 5 / 16 74LVC1G11 Nexperia Single 3-input AND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9. Symbol Conditions -40 °C to +85 °C CPD power dissipation capacitance -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.65 V to 1.95 V 1.5 4.7 17.2 1.5 21.5 ns VCC = 2.3 V to 2.7 V 1.0 3.0 6.2 1.0 7.8 ns VCC = 2.7 V 1.0 3.0 6.0 1.0 7.5 ns VCC = 3.0 V to 3.6 V 1.0 2.6 4.9 1.0 6.2 ns VCC = 4.5 V to 5.5 V 1.0 1.9 3.5 1.0 4.4 ns - 13 - - - pF propagation delay A, B and C to Y; see Fig. 8 tpd [1] [2] [3] Parameter [2] VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of the outputs. 11.1. Waveform and test circuit VI A, B, C input VM GND tPHL VOH tPLH VM Y output VOL 001aac031 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. The input (A, B, C) to output (Y) propagation delays Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 6 / 16 74LVC1G11 Nexperia Single 3-input AND gate VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 9. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VEXT Load VCC VI tr = tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 7 / 16 74LVC1G11 Nexperia Single 3-input AND gate 12. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E y A X HE 6 5 v M A 4 Q pin 1 index A 1 2 e1 A1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT363 JEITA EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 SC-88 Fig. 10. Package outline SOT363 (SC-88) 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 8 / 16 74LVC1G11 Nexperia Single 3-input AND gate Plastic, surface-mounted package (SC-74; TSOP6); 6 leads D SOT457 B E y A X HE 6 5 v M A 4 Q A pin 1 index A1 c 1 2 Lp 3 bp e detail X w M B 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A A1 1.1 0.1 0.9 bp c D E 0.40 0.26 3.1 1.7 0.013 0.25 0.10 2.7 1.3 e 0.95 HE Lp Q 3.0 0.6 0.33 2.5 0.2 0.23 v w y 0.2 0.2 0.1 sot457_po Outline version References IEC JEDEC JEITA SOT457 European projection Issue date 06-03-16 18-11-27 SC-74 Fig. 11. Package outline SOT457 (SC-74; TSOP6) 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 9 / 16 74LVC1G11 Nexperia Single 3-input AND gate SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 L 0.6 0.5 L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig. 12. Package outline SOT886 (XSON6) 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 10 / 16 74LVC1G11 Nexperia Single 3-input AND gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 e1 L 0.3 L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig. 13. Package outline SOT1115 (XSON6) 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 11 / 16 74LVC1G11 Nexperia Single 3-input AND gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig. 14. Package outline SOT1202 (XSON6) 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 12 / 16 74LVC1G11 Nexperia Single 3-input AND gate X2SON6: plastic thermal enhanced extremely thin small outline package; no leads; 6 terminals; body 1.0 x 0.8 x 0.35 mm SOT1255 X A D B A pin 1 ID area E A1 detail X C e1 b (4x) 4 3 y1 C A B v y L (4x) 2 5 Dh (2x) 1 6 e2 0 1 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 D Dh E e1 e2 b L v y y1 max 0.35 0.04 1.05 0.30 0.85 0.30 0.25 nom 0.32 0.02 1.00 0.25 0.80 0.60 0.40 0.25 0.20 0.10 0.05 0.05 0.22 0.17 min 0.30 0.00 0.95 0.22 0.75 sot1255_po Outline version References IEC JEDEC JEITA European projection Issue date 15-07-20 15-07-22 SOT1255 Fig. 15. Package outline SOT1255 (X2SON6) 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 13 / 16 74LVC1G11 Nexperia Single 3-input AND gate 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G11 v.11 20210921 Product data sheet - Modifications: • • • • 74LVC1G11 v.10 20170719 Modifications: • • 74LVC1G11 v.10 Section 2 updated. Type number 74LVC1G11GF (SOT891/XSON6) removed. Table 5: Derating values for Ptot total power dissipation updated. Fig. 11: Package outline drawing SOT457 (SC-74; TSOP6) updated. Product data sheet - 74LVC1G11 v.9 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74LVC1G11 v.9 20161128 Modifications: • 74LVC1G11 v.8 20150917 Modifications: • 74LVC1G11 v.7 20120704 Modifications: • 74LVC1G11 v.6 20111209 Modifications: • 74LVC1G11 v.5 20100730 74LVC1G11 v.4 Product data sheet - 74LVC1G11 v.8 Table 7: The maximum limits for leakage current and supply current have changed. Product data sheet - 74LVC1G11 v.7 Added type number 74LVC1G11GX (SOT1255/X2SON6). Product data sheet - 74LVC1G11 v.6 Package outline drawing of SOT886 (Fig. 12) modified. - 74LVC1G11 v.5 Product data sheet - 74LVC1G11 v.4 20070801 Product data sheet - 74LVC1G11 v.3 74LVC1G11 v.3 20060906 Product data sheet - 74LVC1G11 v.2 74LVC1G11 v.2 20050503 Product data sheet - 74LVC1G11 v.1 74LVC1G11 v.1 20041130 Product data sheet - - 74LVC1G11 Product data sheet Product data sheet Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 14 / 16 74LVC1G11 Nexperia Single 3-input AND gate 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74LVC1G11 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 15 / 16 74LVC1G11 Nexperia Single 3-input AND gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveform and test circuit.......................................... 6 12. Package outline.......................................................... 8 13. Abbreviations............................................................ 14 14. Revision history........................................................14 15. Legal information......................................................15 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 21 September 2021 74LVC1G11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 21 September 2021 © Nexperia B.V. 2021. All rights reserved 16 / 16