74LVC1G17GV,125

74LVC1G17 Single Schmitt trigger buffer Rev. 10 — 29 June 2012 Product data sheet 1. General description The 74LVC1G17 provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined outputs. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 1.65 V to 5.5 V  High noise immunity  Complies with JEDEC standard  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  24 mA output drive (VCC = 3.0 V)  CMOS low power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Unlimited rise and fall times  Inputs accept voltages up to 5 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G17GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74LVC1G17GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753 74LVC1G17GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm SOT886 74LVC1G17GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1  0.5 mm SOT891 74LVC1G17GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9  1.0  0.35 mm 74LVC1G17GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0  1.0  0.35 mm 74LVC1G17GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8  0.8  0.35 mm SOT1226 4. Marking Table 2. Marking codes Type number Marking[1] 74LVC1G17GW VJ 74LVC1G17GV V17 74LVC1G17GM VJ 74LVC1G17GF VJ 74LVC1G17GN VJ 74LVC1G17GS VJ 74LVC1G17GX VJ [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 2 A Y 4 2 mnb150 Fig 1. Logic symbol 74LVC1G17 Product data sheet 4 mnb151 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 2 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer A Y mnb152 Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74LVC1G17 74LVC1G17 n.c. 1 A 2 GND 3 5 4 n.c. 1 6 VCC A 2 5 n.c. GND 3 4 Y VCC Y 001aaf191 001aaf190 Transparent top view Fig 4. Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 74LVC1G17 74LVC1G17 n.c. n.c. 1 6 VCC A 2 5 n.c. GND 3 4 Y 1 VCC 4 Y 3 GND A 2 001aaf402 aaa-003025 Transparent top view Transparent top view Fig 6. 5 Pin configuration SOT891, SOT1115 and SOT1202 Fig 7. Pin configuration SOT1226 (X2SON5) 6.2 Pin description Table 3. Pin description Symbol Pin Description TSSOP5 and X2SON5 XSON6 n.c. 1 1, 5 not connected A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output VCC 5 6 supply voltage 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 3 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 7. Functional description Table 4. Function table[1] Input Output A Y L L H H [1] H = HIGH voltage level; L = LOW voltage level 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA - 100 mA 100 - mA - 250 mW 65 +150 C VI < 0 V [1] VO > VCC or VO < 0 V VO = 0 V to VCC Tamb = 40 C to +125 C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 and X2SON5 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Min Typ Max Unit VCC supply voltage Conditions 1.65 - 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature Active mode VCC = 0 V; Power-down mode 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 0 - 5.5 V 40 - +125 C © NXP B.V. 2012. All rights reserved. 4 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit Tamb = 40 C to +85 C VOH VOL HIGH-level output voltage VI = VT+ or VT LOW-level output voltage IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 - - V IO = 8 mA; VCC = 2.3 V 1.9 - - V IO = 12 mA; VCC = 2.7 V 2.2 - - V IO = 24 mA; VCC = 3.0 V 2.3 - - V IO = 32 mA; VCC = 4.5 V 3.8 - - V VI = VT+ or VT IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V - 0.1 5 A II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 10 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V; per pin - 5 500 A CI input capacitance - 5 - pF IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.7 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V - - 100 A Tamb = 40 C to +125 C VOH VOL II HIGH-level output voltage VI = VT+ or VT LOW-level output voltage input leakage current 74LVC1G17 Product data sheet VI = VT+ or VT VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 5 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer Table 7. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 200 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 200 A ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 5000 A [1] All typical values are measured at maximum VCC and Tamb = 25 C. Table 8. Transfer characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter positive-going threshold voltage VT+ negative-going threshold voltage VT hysteresis voltage VH [1] 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.8 V 0.82 1.0 1.14 0.79 1.14 V VCC = 2.3 V 1.03 1.2 1.40 1.00 1.40 V VCC = 3.0 V 1.29 1.5 1.71 1.26 1.71 V VCC = 4.5 V 1.84 2.1 2.36 1.81 2.36 V VCC = 5.5 V 2.19 2.5 2.79 2.16 2.79 V see Figure 8 and Figure 9 see Figure 8 and Figure 9 VCC = 1.8 V 0.46 0.6 0.75 0.46 0.78 V VCC = 2.3 V 0.65 0.8 0.96 0.65 0.99 V VCC = 3.0 V 0.88 1.0 1.24 0.88 1.27 V VCC = 4.5 V 1.32 1.5 1.84 1.32 1.87 V VCC = 5.5 V 1.58 1.8 2.24 1.58 2.27 V VCC = 1.8 V 0.26 0.4 0.51 0.19 0.51 V VCC = 2.3 V 0.28 0.4 0.57 0.22 0.57 V VCC = 3.0 V 0.31 0.5 0.64 0.25 0.64 V VCC = 4.5 V 0.40 0.6 0.77 0.34 0.77 V VCC = 5.5 V 0.47 0.6 0.88 0.41 0.88 V see Figure 8, Figure 9 and Figure 10 All typical values are measured at Tamb = 25 C. 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 6 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 10.1 Transfer characteristic waveforms VO VT+ VI VH VT− VT− Fig 8. VO VI VH VT+ mnb155 mnb154 Transfer characteristic Fig 9. Definitions of VT+, VT and VH mna641 10 ICC (mA) 8 6 4 2 0 0 1 2 VI (V) 3 VCC = 3.0 V Fig 10. Typical transfer characteristics 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 7 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12. Symbol Parameter propagation delay tpd power dissipation capacitance CPD 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.65 V to 1.95 V 1.0 4.1 11.0 1.0 14.0 ns VCC = 2.3 V to 2.7 V 0.7 2.8 6.5 0.7 8.5 ns VCC = 2.7 V 0.7 3.2 6.5 0.7 8.5 ns VCC = 3.0 V to 3.6 V 0.7 3.0 5.5 0.7 7.0 ns VCC = 4.5 V to 5.5 V 0.7 2.2 5.0 0.7 6.5 ns - 16.6 - - - pF [2] A to Y; see Figure 11 [3] VI = GND to VCC; VCC = 3.3 V [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 12. Waveforms VI VM A input GND t PHL t PLH VOH VM Y output VOL mnb153 Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. The input A to output Y propagation delay times Table 10. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5  VCC 0.5  VCC 2.3 V to 2.7 V 0.5  VCC 0.5  VCC 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 8 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer Table 10. Measurement points …continued Supply voltage Input Output VCC VM VM 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5  VCC 0.5  VCC VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 12. Test circuit for measuring switching times Table 11. Test data Supply voltage Input Load VEXT VCC VI tr = tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC  2.0 ns 30 pF 1 k open 2.3 V to 2.7 V VCC  2.0 ns 30 pF 500  open 2.7 V 2.7 V  2.5 ns 50 pF 500  open 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open 4.5 V to 5.5 V VCC  2.5 ns 50 pF 500  open 13. Application information 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 9 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer mnb156 50 ICC (mA) (1) 40 30 20 (2) 10 0 2 3 4 5 VCC (V) 6 Linear change of VI between 0.8 V to 2.0 V. (1) Positive-going edge. (2) Negative-going edge. Fig 13. Average supply current as a function of supply voltage 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 10 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 14. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 14. Package outline SOT353-1 (TSSOP5) 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 11 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 15. Package outline SOT753 (SC-74A) 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 12 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig 16. Package outline SOT886 (XSON6) 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 13 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 17. Package outline SOT891 (XSON6) 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 14 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig 18. Package outline SOT1115 (XSON6) 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 15 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig 19. Package outline SOT1202 (XSON6) 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 16 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0.8 x 0.35 mm B A D SOT1226 X A E A1 A3 detail X terminal 1 index area e C v w b 1 2 terminal 1 index area C A B C y1 C y k D h 3 L 5 4 0 1 mm scale Dimensions Unit mm A(1) A1 A3 D Dh E b e k L max 0.35 0.04 0.128 0.85 0.30 0.85 0.27 0.27 nom 0.80 0.25 0.80 0.22 0.48 0.22 min 0.20 0.17 0.040 0.75 0.20 0.75 0.17 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Dimension A is including plating thickness. 2. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC JEDEC EIAJ sot1226_po European projection Issue date 12-04-10 12-04-25 SOT1226 Fig 20. Package outline SOT1226 (X2SON5) 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 17 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 15. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 16. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G17 v.10 20120629 Product data sheet - 74LVC1G17 v.9 Modifications: 74LVC1G17 v.9 Modifications: • • Added type number 74LVC1G17GX (SOT1226) Package outline drawing of SOT886 (Figure 16) modified. 20111206 • Product data sheet - 74LVC1G17 v.8 Legal pages updated. 74LVC1G17 v.8 20110920 Product data sheet - 74LVC1G17 v.7 74LVC1G17 v.7 20101110 Product data sheet - 74LVC1G17 v.6 74LVC1G17 v.6 20070827 Product data sheet - 74LVC1G17 v.5 74LVC1G17 v.5 20061006 Product data sheet - 74LVC1G17 v.4 74LVC1G17 v.4 20041130 Product specification - 74LVC1G17 v.3 74LVC1G17 v.3 20041018 Product specification - 74LVC1G17 v.2 74LVC1G17 v.2 20040407 Product specification - 74LVC1G17 v.1 74LVC1G17 v.1 20040324 Product specification - - 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 18 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. 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Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC1G17 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 19 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC1G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 20 of 21 74LVC1G17 NXP Semiconductors Single Schmitt trigger buffer 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Transfer characteristic waveforms . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 June 2012 Document identifier: 74LVC1G17