74LVC1G53
2-channel analog multiplexer/demultiplexer
Rev. 03 — 29 August 2007 Product data sheet
1. General description
The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an active LOW enable input (E). When pin E is HIGH, the switch is turned off. Schmitt-trigger action at the select and enable inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V s Very low ON resistance: x 7.5 Ω (typical) at VCC = 2.7 V x 6.5 Ω (typical) at VCC = 3.3 V x 6 Ω (typical) at VCC = 5 V s Switch current capability of 32 mA s High noise immunity s CMOS low-power consumption s TTL interface compatibility at 3.3 V s Latch-up performance meets requirements of JESD 78 Class I s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101C exceeds 1000 V s Control inputs accepts voltages up to 5 V s Multiple package options s Specified from −40 °C to +85 °C and from −40 °C to +125 °C
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74LVC1G53DP −40 °C to +125 °C 74LVC1G53DC −40 °C to +125 °C 74LVC1G53GT −40 °C to +125 °C 74LVC1G53GM −40 °C to +125 °C TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 SOT765-1 SOT833-1 SOT902-1 Type number
VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm XSON8 XQFN8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2. Marking Marking code V53 V53 V53 V53 Type number 74LVC1G53DC 74LVC1G53DP 74LVC1G53GT 74LVC1G53GM
5. Functional diagram
6 Y1 7 Y0 E 2
S5 Z1
001aad386
Fig 1. Logic symbol
Y0
S Z
Y1
E
001aad387
Fig 2. Logic diagram
74LVC1G53_3 © NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 29 August 2007
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NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
74LVC1G53
Z 1 8 VCC
E
2
7
Y0
74LVC1G53
GND Z E GND GND 1 2 3 4
001aad388
3
6
Y1
8 7 6 5
VCC Y0 Y1 S GND 4 5 S
001aad389
Transparent top view
Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
Fig 4. Pin configuration SOT833-1 (XSON8)
74LVC1G53
terminal 1 index area Y0 1 VCC 8
7
Z
Y1
2
6
E
S
3 4
5
GND
GND
001aag459
Transparent top view
Fig 5. Pin configuration SOT902-1 (XQFN8)
6.2 Pin description
Table 3. Symbol Z E GND GND S
74LVC1G53_3
Pin description Pin SOT505-2, SOT765-1 and SOT833-1 1 2 3 4 5 SOT902-1 7 6 5 4 3 common output or input enable input (active LOW) ground (0 V) ground (0 V) select input
© NXP B.V. 2007. All rights reserved.
Description
Product data sheet
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3 of 22
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
Table 3. Symbol Y1 Y0 VCC
Pin description …continued Pin SOT505-2, SOT765-1 and SOT833-1 6 7 8 SOT902-1 2 1 8 independent input or output independent input or output supply voltage Description
7. Functional description
Table 4. Input S L H X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Function table[1] Channel on E L L H Y0 to Z or Z to Y0 Y1 to Z or Z to Y1 Z (switch off)
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK ISK VSW ISW ICC IGND Tstg Ptot
[1] [2] [3]
Parameter supply voltage input voltage input clamping current switch clamping current switch voltage switch current supply current ground current storage temperature total power dissipation
Conditions
[1]
Min −0.5 −0.5 −50 [2]
Max +6.5 +6.5 ±50 VCC + 0.5 ±50 100 +150 250
Unit V V mA mA V mA mA mA °C mW
VI < −0.5 V or VI > VCC + 0.5 V VI < −0.5 V or VI > VCC + 0.5 V enable and disable mode VSW > −0.5 V or VSW < VCC + 0.5 V
−0.5 −100 −65
Tamb = −40 °C to +125 °C
[3]
-
The minimum input voltage rating may be exceeded if the input current rating is observed. The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. For the TSSOP8 and VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74LVC1G53_3
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Product data sheet
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NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
Table 6. Symbol VCC VI VSW Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V
[1]
[2] [2]
Conditions
Min 1.65 0
Typ -
Max 5.5 5.5 VCC +125 20 10
Unit V V V °C ns/V ns/V
enable and disable mode
[1]
0 −40 -
To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit for the voltage drop across the switch. Applies to control signal levels.
[2]
10. Static characteristics
Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V II input leakage current OFF-state leakage current ON-state leakage current pin S and pin E; VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = VIH or VIL; VCC = 5.5 V; see Figure 6 VI = VIH or VIL; VCC = 5.5 V; see Figure 7
[2]
−40 °C to +85 °C Min 0.65VCC 1.7 2.0 0.7VCC Typ[1] ±0.1 Max 0.35VCC 0.7 0.8 0.3VCC ±2
−40 °C to +125 °C Min 0.65VCC 1.7 2.0 0.7VCC Max 0.7 0.8 0.3VCC ±10 Unit V V V V V V V µA
0.35VCC V
IS(OFF)
[2]
-
±0.1
±5
-
±20
µA
IS(ON)
[2]
-
±0.1
±5
-
±20
µA
ICC
supply current VI = 5.5 V or GND; VSW = GND or VCC; IO = 0 A; VCC = 1.65 V to 5.5 V additional pin S and pin E; VI = VCC − 0.6 V; supply current IO = 0 A; VSW = GND or VCC; VCC = 5.5 V
[2]
-
0.1
10
-
40
µA
∆ICC
[2]
-
5
500
-
5000
µA
74LVC1G53_3
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Product data sheet
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74LVC1G53
2-channel analog multiplexer/demultiplexer
Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter CI CS(OFF) CS(ON) input capacitance OFF-state capacitance ON-state capacitance Conditions −40 °C to +85 °C Min Typ[1] 2.5 6.0 18 Max −40 °C to +125 °C Min Max Unit pF pF pF
[1] [2]
Typical values are measured at Tamb = 25 °C. These typical values are measured at VCC = 3.3 V
10.1 Test circuits
VCC
switch 1 2 switch IS
S VIH VIL
E VIH VIH
VIL or VIH
S Z E
Y0 Y1 GND
1 2
VIH
VI
VO
001aad390
VI = VCC or GND; VO = GND or VCC.
Fig 6. Test circuit for measuring OFF-state leakage current
VCC
switch 1 2 switch
S VIH VIL
E VIL VIL
VIL or VIH IS VIL
VI
S Z E
Y0 Y1 GND
1 2
VO
001aad391
VI = VCC or GND and VO = open circuit.
Fig 7. Test circuit for measuring ON-state leakage current
74LVC1G53_3
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Product data sheet
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NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
10.2 ON resistance
Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14. Symbol RON(peak) Parameter Conditions −40 °C to +85 °C Min ON resistance (peak) VI = GND to VCC; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(rail) ON resistance (rail) VI = GND; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V VI = VCC; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(flat) ON resistance (flatness) VI = GND to VCC ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V
[1] [2] Typical values are measured at Tamb = 25 °C and nominal VCC. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature.
[2]
−40 °C to +125 °C Unit Min Max 195 45 38 30 23 27 24 21 18 15 45 30 27 23 15 Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω
Typ[1] 34.0 12.0 10.4 7.8 6.2 8.2 7.1 6.9 6.5 5.8 10.4 7.6 7.0 6.1 4.9 26.0 5.0 3.5 2.0 1.5
Max 130 30 25 20 15 18 16 14 12 10 30 20 18 15 10 -
-
74LVC1G53_3
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Product data sheet
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NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
10.3 ON resistance test circuit and graphs
VSW
VCC
switch 1 2
S VIL VIH
E VIL VIL
VIL or VIH
S Z E
Y0 Y1 GND
1 switch 2
VIL
VI
ISW
001aad392
RON = VSW / ISW.
Fig 8. Test circuit for measuring ON resistance
40 RON (Ω) 30
mna673
(1)
20
(2) (3)
10
(4) (5)
0 0 1 2 3 4 VI (V) 5
(1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V.
Fig 9. Typical ON resistance as a function of input voltage; Tamb = 25 °C
74LVC1G53_3
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Product data sheet
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NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
55 RON (Ω) 45
001aaa712
15 RON (Ω) 13
001aaa708
35
(4) (3) (2) (1)
11
(1) (2)
25
9
(3) (4)
15
7
5 0 0.4 0.8 1.2 1.6 VI (V) 2.0
5 0 0.5 1.0 1.5 2.0 VI (V) 2.5
(1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C.
(1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C.
Fig 10. ON resistance as a function of input voltage; VCC = 1.8 V
Fig 11. ON resistance as a function of input voltage; VCC = 2.5 V
13 RON (Ω) 11
001aaa709
10 RON (Ω) 8
001aaa710
(1)
(1) (2)
9
(2) (3)
6
(3)
7
(4) (4)
5 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V)
4 0 1 2 3 VI (V) 4
(1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C.
(1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C.
Fig 12. ON resistance as a function of input voltage; VCC = 2.7 V
Fig 13. ON resistance as a function of input voltage; VCC = 3.3 V
74LVC1G53_3
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Product data sheet
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NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
7 RON (Ω) 6
001aaa711
5
(1) (2)
4
(3)
(4)
3 0 1 2 3 4 VI (V) 5
(1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C.
Fig 14. ON resistance as a function of input voltage; VCC = 5.0 V
11. Dynamic characteristics
Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17. Symbol Parameter tpd Conditions
[2][3]
−40 °C to +85 °C Min Typ[1] Max 2 1.2 1.0 0.8 0.6
−40 °C to +125 °C Unit Min Max 2.5 1.5 1.25 1.0 0.8 ns ns ns ns ns
propagation delay Z to Yn or Yn to Z; see Figure 15 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
-
74LVC1G53_3
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Product data sheet
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74LVC1G53
2-channel analog multiplexer/demultiplexer
Table 9. Dynamic characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17. Symbol Parameter ten enable time Conditions S to Z or Yn; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V E to Z or Yn; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tdis disable time S to Z or Yn; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V E to Z or Yn; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
[1] [2] [3] [4] [5] Typical values are measured at Tamb = 25 °C and nominal VCC. tpd is the same as tPLH and tPHL. propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). ten is the same as tPZH and tPZL tdis is the same as tPLZ and tPHZ
[5] [5] [4] [4]
−40 °C to +85 °C Min 2.6 1.9 1.9 1.8 1.3 1.9 1.4 1.1 1.2 1.0 2.1 1.4 1.4 1.1 1.0 2.3 1.2 1.4 2.0 1.3 Typ[1] 6.7 4.1 4.0 3.4 2.6 4.0 2.5 2.6 2.2 1.7 6.8 3.7 4.9 4.0 2.9 5.6 3.2 4.0 3.7 2.9 Max 10.3 6.4 5.5 5.0 3.8 7.3 4.4 3.9 3.8 2.6 10.0 6.1 6.2 5.4 3.8 8.6 4.8 5.2 5.0 3.8
−40 °C to +125 °C Unit Min 2.6 1.9 1.8 1.8 1.3 1.9 1.4 1.1 1.2 1.0 2.1 1.4 1.4 1.1 1.0 2.3 1.2 1.4 2.0 1.3 Max 12.9 8.0 7.0 6.3 4.8 9.2 5.5 4.9 4.8 3.3 12.5 7.7 7.8 6.8 4.8 11.0 6.0 6.5 6.3 4.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74LVC1G53_3
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Product data sheet
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74LVC1G53
2-channel analog multiplexer/demultiplexer
11.1 Waveforms and test circuits
VI Yn or Z input GND tPLH VOH Z or Yn output VOL
001aac361
VM
VM
tPHL
VM
VM
Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. Input (Yn or Z) to output (Z or Yn) propagation delays
VI S, E input GND tPLZ Z, Yn output LOW to OFF OFF to LOW VCC VX tPHZ VY VM GND switch enabled switch disabled switch enabled
001aad393
VM tPZL
VM tPZH
VOL output HIGH to OFF OFF to HIGH VOH
Z, Yn
Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times Table 10. VCC 1.65 V to 2.7 V 2.7 V to 5.5 V Measurement points Input VM 0.5VCC 0.5VCC Output VM 0.5VCC 0.5VCC VX VOL + 0.15 V VOL + 0.3 V VY VOH − 0.15 V VOH − 0.3 V
Supply voltage
74LVC1G53_3
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Product data sheet
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74LVC1G53
2-channel analog multiplexer/demultiplexer
VEXT VCC VI VO DUT
RT CL RL RL
G
mna616
Test data is given in Table 11. Definitions test circuit: RT = Termination resistance (should be equal to output impedance Zo of the pulse generator). CL = Load capacitance (including jig and probe capacitance). RL = Load resistance. VEXT = External voltage for measuring switching times.
Fig 17. Load circuit for switching times Table 11. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC VCC VCC VCC tr, tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2VCC 2VCC 2VCC 2VCC 2VCC
Supply voltage
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C. Symbol THD Parameter total harmonic distortion Conditions fi = 600 Hz to 20 kHz; RL = 600 Ω; CL = 50 pF; VI = 0.5 V (p-p); see Figure 18 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V f(-3dB) −3 dB frequency response RL = 50 Ω; CL = 5 pF; see Figure 19 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V 200 300 300 300 MHz MHz MHz MHz 0.260 0.078 0.078 0.078 % % % % Min Typ Max Unit
74LVC1G53_3
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Product data sheet
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74LVC1G53
2-channel analog multiplexer/demultiplexer
Table 12. Additional dynamic characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C. Symbol αiso Parameter isolation (OFF-state) Conditions RL = 50 Ω; CL = 5 pF; fi = 10 MHz; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V Qinj charge injection CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω; fi = 1 MHz; RL = 1 MΩ; see Figure 21 VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 4.5 V VCC = 5.5 V 3.3 4.1 5.0 6.4 7.5 pC pC pC pC pC −42 −42 −40 −40 dB dB dB dB Min Typ Max Unit
11.3 Test circuits
VCC 0.5VCC
RL
switch 1 2
S VIL VIH
E VIL VIL
VIL or VIH
S
0.1 µF
Y0 Y1 E
1 2
switch
10 µF
Z
VIL
fi 600 Ω CL
D
GND
001aad394
Fig 18. Test circuit for measuring total harmonic distortion
VCC
0.5VCC
RL
switch 1 2
S VIL VIH
E VIL VIL
VIL or VIH
S
0.1 µF
Y0 Y1 E
1 2
switch
Z
VIL
fi 50 Ω CL
dB
GND
001aad395
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB.
Fig 19. Test circuit for measuring the frequency response when switch is in ON-state
74LVC1G53_3
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74LVC1G53
2-channel analog multiplexer/demultiplexer
0.5VCC VCC
RL
0.5VCC switch
RL
S VIH VIL
E VIH VIH
1 2
VIL or VIH
S
0.1 µF
Y0 Y1 E
1 2
switch
Z
VIH
fi 50 Ω CL
dB
GND
001aad396
Adjust fi voltage to obtain 0 dBm level at input.
Fig 20. Test circuit for measuring isolation (OFF-state)
VCC S Z E VIL VI G
Rgen
Y0 Y1
1 2
switch
VO
RL
CL
Vgen
GND
001aad398
a. Test circuit
logic (S) off input
on
off
VO
∆VO
001aac478
b. Input and output pulse definitions
Qinj = ∆VO × CL. ∆VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage.
Fig 21. Test circuit for measuring charge injection
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2-channel analog multiplexer/demultiplexer
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
θ
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0°
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
Fig 22. Package outline SOT505-2 (TSSOP8)
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Product data sheet
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74LVC1G53
2-channel analog multiplexer/demultiplexer
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) θ Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0°
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
Fig 23. Package outline SOT765-1 (VSSOP8)
74LVC1G53_3 © NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 29 August 2007
17 of 22
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
1
2
3
b 4 4× L
(2)
L1
e
8 e1
7 e1
6 e1
5
8×
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09
Fig 24. Package outline SOT833-1 (XSON8)
74LVC1G53_3 © NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 29 August 2007
18 of 22
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D terminal 1 index area
B
A
E
A A1
detail X
L1 L
e
4
e ∅v M C A B ∅w M C
5
C y1 C y
3
metal area not for soldering
2 6
b
e1
e1
7 1
terminal 1 index area
8
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05
OUTLINE VERSION SOT902-1
REFERENCES IEC --JEDEC MO-255 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-11-16 05-11-25
Fig 25. Package outline SOT902-1 (XQFN8)
74LVC1G53_3 © NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 29 August 2007
19 of 22
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
13. Abbreviations
Table 13. Acronym CMOS TTL HBM ESD MM CDM DUT Abbreviations Description Complementary Metal Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Charged Device Model Device Under Test
14. Revision history
Table 14. Revision history Release date 20070829 Data sheet status Product data sheet Change notice Supersedes 74LVC1G53_2 Document ID 74LVC1G53_3 Modifications:
• • • • • •
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74LVC1G53GM (XQFN8/SOT902-1 package). Section 2 “Features”: Added: Switch handling capability of 32 mA. Section 10 “Static characteristics”: Changed: Conditions for input leakage and supply current. Section 11.2 “Additional dynamic characteristics”: Removed: Crosstalk between switches removed from additional characteristics table. Changed: Typical values of the charge injection.
74LVC1G53_2 74LVC1G53_1
20060410 20060110
Product data sheet Product data sheet
-
74LVC1G53_1 -
74LVC1G53_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 29 August 2007
20 of 22
NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC1G53_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 29 August 2007
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NXP Semiconductors
74LVC1G53
2-channel analog multiplexer/demultiplexer
17. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms and test circuits . . . . . . . . . . . . . . 12 Additional dynamic characteristics . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 August 2007 Document identifier: 74LVC1G53_3