74LVC1G57

74LVC1G57 Low-power configurable multiple function gate Rev. 03 — 19 July 2007 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. All inputs (A, B and C) have Schmitt trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2. Features s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C s s s s s s s s NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC1G57GW 74LVC1G57GV 74LVC1G57GM 74LVC1G57GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name SC-88 SC-74 XSON6 XSON6 Description plastic surface-mounted package; 6 leads plastic surface-mounted package (TSOP6); 6 leads plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm Version SOT363 SOT457 SOT886 SOT891 Type number 4. Marking Table 2. Marking Marking code YC V57 YC YC Type number 74LVC1G57GW 74LVC1G57GV 74LVC1G57GM 74LVC1G57GF 5. Functional diagram 3 4 B 1 Y A C 6 001aab583 Fig 1. Logic symbol 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 2 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 6. Pinning information 6.1 Pinning 74LVC1G57 74LVC1G57 B GND 1 2 6 5 C GND VCC A A 3 001aaf138 B 1 6 C B GND 74LVC1G157 1 2 3 6 5 4 C VCC Y 2 5 VCC 3 4 Y A 4 Y 001aaf139 001aaf140 Transparent top view Transparent top view Fig 2. Pin configuration SOT363 (SC-88) and SOT457 (SC-74) Fig 3. Pin configuration SOT886 (XSON6) Fig 4. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Symbol B GND A Y VCC C Pin description Pin 1 2 3 4 5 6 Description data input ground (0 V) data input data output supply voltage data input 7. Functional description Table 4. Input C L L L L H H H H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output B L L H H L L H H A L H L H L H L H Y H L H L L L H H 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 3 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 7.1 Logic configurations Table 5. Function selection table Figure see Figure 5 see Figure 8 see Figure 6 and Figure 7 see Figure 6 and Figure 7 see Figure 8 see Figure 5 see Figure 9 see Figure 10 see Figure 11 Logic function 2-input AND 2-input AND with both inputs inverted 2-input NAND with inverted input 2-input OR with inverted input 2-input NOR 2-input NOR with both inputs inverted 2-input XNOR Inverter Buffer VCC B C Y B 1 2 B C Y 3 6 5 4 Y B C Y C B C Y B 1 2 3 6 5 4 Y C VCC 001aab584 001aab585 Fig 5. 2-input AND gate or 2-input NOR gate with both inputs inverted Fig 6. 2-input NAND gate with input B inverted or 2-input OR gate with inverted C input VCC VCC A C Y A C 1 2 A C Y A 3 6 5 4 Y C A C Y A Y 1 2 3 6 5 4 Y C 001aab587 001aab586 Fig 7. 2-input NAND gate with input C inverted or 2-input OR gate with inverted A input Fig 8. 2-input NOR gate or 2-input AND gate with both inputs inverted VCC VCC B B C Y 1 2 3 6 5 4 Y A Y A 001aab588 001aab589 C 1 2 3 6 5 4 Y Fig 9. 2-input XNOR gate Fig 10. Inverter 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 4 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate VCC B B Y 1 2 3 6 5 4 Y 001aab590 Fig 11. Buffer 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [1][2] [1][2] Max +6.5 +6.5 ±50 +6.5 +6.5 ±50 +100 +150 250 Unit V mA V mA V V mA mA mA °C mW VO > VCC or VO < 0 V Active mode Power-down mode VO = 0 V to VCC −0.5 −0.5 −100 −65 Tamb = −40 °C to +125 °C [3] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For SC-88 and SC-74 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 7. Symbol VCC VI VO Tamb Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature Active mode VCC = 0 V; Power-down mode Conditions Min 1.65 0 0 0 −40 Typ Max 5.5 5.5 VCC 5.5 +125 Unit V V V V °C 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 5 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage Conditions VI = VCC or GND IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V VOH HIGH-level output voltage VI = VCC or GND IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V II IOFF input leakage current power-off leakage current supply current additional supply current input capacitance Typical values are measured at maximum VCC and Tamb = 25 °C. −40 °C to +85 °C Min VCC − 0.1 1.2 1.9 2.2 2.3 3.8 Typ[1] ±0.1 ±0.1 Max 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 −40 °C to +125 °C Min VCC − 0.1 0.95 1.7 1.9 2.0 3.4 Max 0.1 0.7 0.45 0.6 0.8 0.8 ±100 ±200 Unit V V V V V V V V V V V V µA µA VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI or VO = 5.5 V; VCC = 0 V ICC ∆ICC CI VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 0.1 5 2.5 10 500 - - 200 5000 - µA µA pF [1] 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 6 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 13. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 6.0 3.5 4.2 3.8 3.0 22 Max 14.4 8.3 8.5 6.3 5.1 - −40 °C to +125 °C Unit Min 1.0 0.5 0.5 0.5 0.5 Max 18 10.4 10.6 7.9 6.4 ns ns ns ns ns pF propagation delay A, B, C to Y; see Figure 12 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.0 0.5 0.5 0.5 0.5 [3] CPD power dissipation capacitance VCC = 3.3 V; VI = GND to VCC - [1] [2] [3] Typical values are measured at nominal VCC and at Tamb = 25 °C. tpd is the same as tPLH and tPHL CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 12. Waveforms VI A, B, C input GND t PHL VOH Y output VOL t PLH VOH Y output VOL VM VM t PHL VM VM t PLH VM VM 001aab593 Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. Input A, B and C to output Y propagation delay times 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 7 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate Table 10. VCC Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC VI VCC VCC 2.7 V 2.7 V VCC Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VEXT VCC VI VO DUT RT CL RL RL G mna616 Measurement points are given in Table 11. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Load circuit for switching times Table 11. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VI VCC VCC 2.7 V 2.7 V VCC tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open Supply voltage 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 8 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 13. Transfer characteristics Table 12. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VT+ positive-going threshold voltage Conditions see Figure 14, Figure 15, Figure 16 and Figure 17 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V VT− negative-going threshold voltage see Figure 14, Figure 15, Figure 16 and Figure 17 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V VH hysteresis voltage (VT+ − VT−) see Figure 14, Figure 15, Figure 16 and Figure 17 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V [1] Typical values are measured at Tamb = 25 °C. −40 °C to +85 °C Min Typ[1] Max −40 °C to +125 °C Unit Min Max 0.70 1.11 1.50 2.16 2.61 1.02 1.42 1.79 2.52 2.99 1.20 1.60 2.00 2.74 3.33 0.67 1.08 1.47 2.13 2.58 1.20 1.60 2.00 2.74 3.33 V V V V V 0.30 0.58 0.80 1.21 1.45 0.53 0.77 1.04 1.55 1.86 0.72 1.00 1.30 1.90 2.29 0.30 0.58 0.80 1.21 1.45 0.75 1.03 1.33 1.93 2.32 V V V V V 0.30 0.40 0.50 0.71 0.71 0.48 0.64 0.75 0.97 1.13 0.62 0.80 1.00 1.20 1.40 0.23 0.34 0.44 0.65 0.65 0.62 0.80 1.00 1.20 1.40 V V V V V 14. Waveforms transfer characteristics VO VT+ VI VT− VH VH VT− VT+ VI mna207 VO mna208 VT+ and VT− limits are at 70 % and 20 %. Fig 14. Transfer characteristic Fig 15. Definition of VT+, VT− and VH 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 9 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate VO VI VT+ VT− VH VH VT− VT+ VI mnb154 VO mnb155 VT+ and VT− limits are at 70 % and 20 %. Fig 16. Transfer characteristic Fig 17. Definition of VT+, VT− and VH 16 I CC (mA) 12 001aab594 8 4 0 0 1 2 VI (V) 3 Fig 18. Typical 74LVC1G57 transfer characteristic; VCC = 3.0 V 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 10 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 15. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 19. Package outline SOT363 (SC-88) 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 11 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate Plastic surface-mounted package (TSOP6); 6 leads SOT457 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 c 1 2 3 Lp e bp wM B detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT457 REFERENCES IEC JEDEC JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 20. Package outline SOT457 (SC-74) 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 12 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 21. Package outline SOT886 (XSON6) 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 13 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 22. Package outline SOT891 (XSON6) 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 14 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 16. Abbreviations Table 13. Acronym CMOS TTL HBM ESD MM DUT Abbreviations Description Complementary Metal Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Device Under Test 17. Revision history Table 14. Revision history Release date 20070719 Data sheet status Product data sheet Change notice Supersedes 74LVC1G57_2 Document ID 74LVC1G57_3 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 10 “Static characteristics”: Changed: Conditions for input leakage current and supply current. New package outline drawing for XSON6/SOT891. Product data sheet Product data sheet 74LVC1G57_1 - 74LVC1G57_2 74LVC1G57_1 20060911 20040906 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 15 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC1G57_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 19 July 2007 16 of 17 NXP Semiconductors 74LVC1G57 Low-power configurable multiple function gate 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Transfer characteristics. . . . . . . . . . . . . . . . . . . 9 Waveforms transfer characteristics . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 July 2007 Document identifier: 74LVC1G57_3