74LVC2G02GM

74LVC2G02 Dual 2-input NOR gate Rev. 05 — 4 September 2007 Product data sheet 1. General description The 74LVC2G02 provides a 2-input NOR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features s s s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: x HBM EIA/JESD22-A114E exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C s s s s s s NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC2G02DP 74LVC2G02DC 74LVC2G02GT 74LVC2G02GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP8 VSSOP8 XSON8 XQFN8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-1 4. Marking Table 2. Marking Marking code V02 V02 V02 V02 Type number 74LVC2G02DP 74LVC2G02DC 74LVC2G02GT 74LVC2G02GM 5. Functional diagram 1 1 2 5 6 1A 1B 2A 2B 1Y 7 2 ≥1 7 2Y 3 5 6 ≥1 3 mna716 mna717 Fig 1. Logic symbol Fig 2. IEC logic symbol B Y A mna105 Fig 3. Logic diagram (one gate) 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 2 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 6. Pinning information 6.1 Pinning 74LVC2G02 1A 1B 2Y GND 1 2 3 4 001aab642 8 7 6 5 VCC 1Y 2B 2A Fig 4. Pin configuration TSSOP8 and VSSOP8 74LVC2G02 74LVC2G02 1A 1 8 VCC terminal 1 index area 1Y 1 VCC 8 7 1A 1B 2 7 1Y 2B 2 6 1B 2Y 3 6 2B 2A 3 4 5 2Y GND GND 4 5 2A 001aae971 001aab643 Transparent top view Transparent top view Fig 5. Pin configuration XSON8 Fig 6. Pin configuration XQFN8 6.2 Pin description Table 3. Symbol 1A 1B 2Y GND 2A 2B 1Y VCC Pin description Pin TSSOP8, VSSOP8 1 2 3 4 5 6 7 8 XSON8 1 2 3 4 5 6 7 8 XQFN8 7 6 5 4 3 2 1 8 data input data input data output ground (0 V) data input data input data output supply voltage Description 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 3 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 7. Functional description Table 4. Input nA L X H [1] Function table[1] Output nB L H X nY H L L H = HIGH voltage level; L = LOW voltage level; X = don’t care 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions [1] Min −0.5 −0.5 −0.5 −0.5 −50 −100 −65 Max +6.5 +6.5 VCC + 0.5 +6.5 ±50 ±50 100 +150 300 Unit V V V V mA mA mA mA mA °C mW Active mode Power-down mode VI < 0 V VO < 0 V or VO > VCC VO = 0 V to VCC [1] [1][2] Tamb = −40 °C to +125 °C [3] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition. For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 and XQFN packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Active mode Power-down mode Conditions Min 1.65 0 0 0 −40 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V °C ns/V ns/V 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 4 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH °C[1] VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF ICC ∆ICC CI VIH input leakage current supply current additional supply current input capacitance HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 74LVC2G02_5 Conditions Min Typ Max 0.7 0.8 0.3 × VCC 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 10 500 0.7 0.8 0.3 × VCC Unit V V V V V V V V V V V V V V V V V V V µA µA µA µA pF V V V V V V V 5 of 15 HIGH-level input voltage 0.65 × VCC 1.7 2.0 0.7 × VCC VCC − 0.1 1.2 1.9 2.2 2.3 3.8 1.53 2.13 2.50 2.60 4.10 0.08 0.14 0.19 0.37 0.43 ±0.1 ±0.1 0.1 5 2.5 0.35 × VCC V VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V power-off leakage current VI or VO = 5.5 V; VCC = 0 V Tamb = −40 °C to +125 °C 0.65 × VCC 1.7 2.0 0.7 × VCC - 0.35 × VCC V © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH Conditions IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF ICC ∆ICC input leakage current supply current additional supply current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V power-off leakage current VI or VO = 5.5 V; VCC = 0 V 0.1 0.70 0.45 0.60 0.80 0.80 ±20 ±20 40 5000 V V V V V V µA µA µA µA Min VCC − 0.1 0.95 1.7 1.9 2.0 3.4 Typ Max Unit V V V V V V HIGH-level output voltage VI = VIH or VIL [1] All typical values are measured at Tamb = 25 °C. 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 6 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 8. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 3.8 2.4 3.2 2.4 1.8 14 Max 8.9 5.4 6.0 4.9 4.3 - −40 °C to +125 °C Unit Min 1.2 0.8 0.8 0.6 0.6 Max 11.2 6.8 7.5 6.2 5.5 ns ns ns ns ns pF propagation delay nA, nB to nY; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.2 0.8 0.8 0.6 0.6 [3] CPD power dissipation capacitance per gate; VI = GND to VCC - [1] [2] [3] Typical values are measured at nominal VCC and at Tamb = 25 °C. tpd is the same as tPLH and tPHL CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 12. Waveforms VI nA, nB input GND t PHL VOH nY output VOL VM 001aae972 VM t PLH Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Input (nA, nB) to output (nY) propagation delays 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 7 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate Table 9. VCC Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO 001aae235 Test data is given in Table 10. Definitions for test circuit: RL = Load resistor CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to output impedance Zo of the pulse generator VEXT = Test voltage for switching times Fig 8. Load circuitry for switching times Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open Supply voltage 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 8 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 9. Package outline SOT505-2 (TSSOP8) 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 9 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 10. Package outline SOT765-1 (VSSOP8) 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 10 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 11. Package outline SOT833-1 (XSON8) 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 11 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-16 05-11-25 Fig 12. Package outline SOT902-1 (XQFN8) 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 12 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 14. Abbreviations Table 11. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 12. Revision history Release date 20070904 Data sheet status Product data sheet Change notice Supersedes 74LVC2G02_4 Document ID 74LVC2G02_5 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. In Section 10 “Static characteristics”, changed conditions for input leakage and supply current. Product data sheet Product specification Product specification Product specification 74LVC2G02_3 74LVC2G02_2 74LVC2G02_1 - 74LVC2G02_4 74LVC2G02_3 74LVC2G02_2 74LVC2G02_1 20060515 20050201 20040915 20031015 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 13 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC2G02_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 4 September 2007 14 of 15 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 September 2007 Document identifier: 74LVC2G02_5