74LVC2G08GN

74LVC2G08 Dual 2-input AND gate Rev. 9 — 20 October 2010 Product data sheet 1. General description The 74LVC2G08 provides a 2-input AND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC2G08DP 74LVC2G08DC 74LVC2G08GT 74LVC2G08GF 74LVC2G08GD 74LVC2G08GM 74LVC2G08GN 74LVC2G08GS −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name TSSOP8 VSSOP8 XSON8 XSON8 XSON8U XQFN8U XSON8 XSON8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm SOT1089 plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT902-1 SOT1116 SOT1203 4. Marking Table 2. Marking codes Marking code[1] V08 V08 V08 VE V08 V08 VE VE Type number 74LVC2G08DP 74LVC2G08DC 74LVC2G08GT 74LVC2G08GF 74LVC2G08GD 74LVC2G08GM 74LVC2G08GN 74LVC2G08GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 2 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 5. Functional diagram & 1A 1B 2A 2B 1Y 2Y & 001aah788 001aah789 Fig 1. Logic symbol Fig 2. IEC logic symbol A Y B mna221 Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74LVC2G08 1A 1 8 VCC 1B 2 7 1Y 74LVC2G08 1A 1B 2Y GND 1 2 3 4 001aae981 8 7 6 5 VCC 1Y 2B 2A 2Y 3 6 2B GND 4 5 2A 001aae982 Transparent top view Fig 4. Pin configuration SOT505-2 and SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 3 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 74LVC2G08 terminal 1 index area 1Y 1 VCC 8 74LVC2G08 1A 1B 2Y GND 1 2 3 4 8 7 6 5 VCC 7 1A 2B 1Y 2B 2A 2A 2 6 1B 3 4 5 2Y GND 001aae983 001aai245 Transparent top view Transparent top view Fig 6. Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-1 6.2 Pin description Table 3. Symbol Pin description Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 1A 1B 2Y GND 2A 2B 1Y VCC 1 2 3 4 5 6 7 8 SOT902-1 7 6 5 4 3 2 1 8 data input data input data output ground (0 V) data input data input data output supply voltage Description 7. Functional description Table 4. Input nA L X H [1] Function table[1] Output nB X L H nY L L H H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 4 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions [1] Min −0.5 −0.5 −0.5 −0.5 −50 −100 −65 Max +6.5 +6.5 VCC + 0.5 +6.5 ±50 ±50 100 +150 300 Unit V V V V mA mA mA mA mA °C mW Active mode Power-down mode VI < 0 V VO < 0 V or VO > VCC VO = 0 V to VCC [1] [1][2] Tamb = −40 °C to +125 °C [3] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition. For TSSOP8 package: above 55 °C the value of Ptot derates linearly at 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly at 8 mW/K. For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb Δt/ΔV Operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Active mode Power-down mode Conditions Min 1.65 0 0 0 −40 Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V °C ns/V ns/V 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 5 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH °C[1] VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 μA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF ICC ΔICC Ci VIH input leakage current supply current additional supply current input capacitance HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 74LVC2G08 All information provided in this document is subject to legal disclaimers. Conditions Min Typ Max 0.7 0.8 0.3 × VCC 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 10 500 0.7 0.8 0.3 × VCC Unit V V V V V V V V V V V V V V V V V V V μA μA μA μA pF V V V V V V V 6 of 21 HIGH-level input voltage 0.65 × VCC 1.7 2.0 0.7 × VCC VCC − 0.1 1.2 1.9 2.2 2.3 3.8 1.53 2.13 2.50 2.60 4.10 0.08 0.14 0.19 0.37 0.43 ±0.1 ±0.1 0.1 5 2.5 0.35 × VCC V VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V power-off leakage current VI or VO = 5.5 V; VCC = 0 V Tamb = −40 °C to +125 °C 0.65 × VCC 1.7 2.0 0.7 × VCC - 0.35 × VCC V © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH Conditions IO = −100 μA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF ICC ΔICC input leakage current supply current additional supply current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V power-off leakage current VI or VO = 5.5 V; VCC = 0 V 0.1 0.70 0.45 0.60 0.80 0.80 ±20 ±20 40 5000 V V V V V V μA μA μA μA Min VCC − 0.1 0.95 1.7 1.9 2.0 3.4 Typ Max Unit V V V V V V HIGH-level output voltage VI = VIH or VIL [1] All typical values are measured at Tamb = 25 °C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 3.2 2.2 2.5 2.1 1.7 Max 9.0 5.1 5.3 4.7 3.8 −40 °C to +125 °C Unit Min 1.0 0.5 1.0 0.5 0.5 Max 11.3 6.4 6.7 5.9 4.8 ns ns ns ns ns propagation delay nA, nB to nY; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.0 0.5 1.0 0.5 0.5 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 7 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter CPD power dissipation capacitance Conditions per gate; VI = GND to VCC [3] −40 °C to +85 °C Min Typ[1] 14.4 Max - −40 °C to +125 °C Unit Min Max pF [1] [2] [3] Typical values are measured at nominal VCC and at Tamb = 25 °C. tpd is the same as tPLH and tPHL CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 12. Waveforms VI nA, nB input GND t PHL VOH nY output VOL VM mna224 VM t PLH Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 9. VCC Input (nA, nB) to output (nY) propagation delays Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 8 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO 001aae235 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to output impedance Zo of the pulse generator VEXT = Test voltage for switching times Fig 9. Table 10. VCC Test circuit for measuring switching times Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 9 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 10. Package outline SOT505-2 (TSSOP8) 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 10 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 11. Package outline SOT765-1 (VSSOP8) 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 11 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 12. Package outline SOT833-1 (XSON8) 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 12 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm E SOT1089 terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b4 5 e1 1 terminal 1 index area 8 L1 0 0.5 scale 1 mm X Dimensions Unit mm max nom min A(1) 0.5 A1 b D E e e1 L L1 0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.27 0.32 0.12 1.30 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 References IEC JEDEC MO-252 JEITA European projection sot1089_po Issue date 10-04-09 10-04-12 Fig 13. Package outline SOT1089 (XSON8) 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 13 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 14. Package outline SOT996-2 (XSON8U) 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 14 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 15. Package outline SOT902-1 (XQFN8U) 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 15 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116 1 2 3 b 4 (4×)(2) L1 e L 8 e1 7 e1 6 e1 5 (8×)(2) A1 A D E terminal 1 index area 0 Dimensions Unit mm A(1) A1 b D E e e1 0.3 L L1 0.5 scale 1 mm max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1116 References IEC JEDEC JEITA European projection sot1116_po Issue date 10-04-02 10-04-07 Fig 16. Package outline SOT1116 (XSON8) 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 16 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 1 2 3 4 (4×)(2) L1 e L 8 e1 7 e1 6 e1 5 (8×)(2) A1 A D E terminal 1 index area 0 Dimensions Unit mm A(1) A1 b D E e e1 L L1 0.5 scale 1 mm max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1203 References IEC JEDEC JEITA European projection sot1203_po Issue date 10-04-02 10-04-06 Fig 17. Package outline SOT1203 (XSON8) 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 17 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 14. Abbreviations Table 11. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 12. Revision history Release date 20101020 Data sheet status Product data sheet Change notice Supersedes 74LVC2G08 v.8 Document ID 74LVC2G08 v.9 Modifications: • • • Added type number 74LVC2G08GF (SOT1089/XSON8 package) Added type number 74LVC2G08GN (SOT1116/XSON8 package). Added type number 74LVC2G08GS (SOT1203/XSON8 package). Product data sheet Product data sheet Product data sheet Product data sheet Product specification Product specification Product specification Product specification 74LVC2G08 v.7 74LVC2G08 v.6 74LVC2G08 v.5 74LVC2G08 v.4 74LVC2G08 v.3 74LVC2G08 v.2 74LVC2G08 v.1 - 74LVC2G08 v.8 74LVC2G08 v.7 74LVC2G08 v.6 74LVC2G08 v.5 74LVC2G08 v.4 74LVC2G08 v.3 74LVC2G08 v.2 74LVC2G08 v.1 20080609 20080303 20070904 20060515 20050201 20040915 20031020 20030825 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 18 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 19 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC2G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 9 — 20 October 2010 20 of 21 NXP Semiconductors 74LVC2G08 Dual 2-input AND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 October 2010 Document identifier: 74LVC2G08