74LVC2G66GMV66

74LVC2G66 Bilateral switch Rev. 5 — 16 June 2010 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 7.5 Ω (typical) at VCC = 2.7 V 6.5 Ω (typical) at VCC = 3.3 V 6 Ω (typical) at VCC = 5 V Switch current capability of 32 mA High noise immunity CMOS low power consumption TTL interface compatibility at 3.3 V Latch-up performance meets requirements of JESD78 Class I ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Enable input accepts voltages up to 5.5 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74LVC2G66 Bilateral switch 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC2G66DP 74LVC2G66DC 74LVC2G66GT 74LVC2G66GD 74LVC2G66GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP8 VSSOP8 XSON8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm Version SOT505-2 SOT765-1 SOT833-1 SOT996-2 SOT902-1 Type number XSON8U plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 × 2 × 0.5 mm XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm 4. Marking Table 2. Marking codes Marking code[1] V66 V66 V66 V66 V66 Type number 74LVC2G66DP 74LVC2G66DC 74LVC2G66GT 74LVC2G66GD 74LVC2G66GM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 # 1 X1 1 # 001aah807 1 X1 001aah808 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 2 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch nZ nY nE VCC mna658 Fig 3. Logic diagram (one switch) 6. Pinning information 6.1 Pinning 74LVC2G66 1Y 1 8 VCC 1Z 2 7 1E 74LVC2G66 2E 1Y 1Z 2E GND 1 2 3 4 001aaa529 3 6 2Z 8 7 6 5 VCC 1E 2Z 2Y GND 4 5 2Y 001aaf567 Transparent top view Fig 4. Pin configuration SOT505-2 and SOT765-1 Fig 5. Pin configuration SOT833-1 74LVC2G66 terminal 1 index area 1E 1 VCC 8 74LVC2G66 1Y 1Z 2E GND 1 2 3 4 8 7 6 5 VCC 7 1Y 2Z 1E 2Z 2Y 2Y 2 6 1Z 3 4 5 2E GND 001aaf568 001aai248 Transparent top view Transparent top view Fig 6. Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-1 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 3 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 6.2 Pin description Table 3. Symbol Pin description Pin SOT505-2, SOT765-1, SOT996-2 and SOT833-1 1Y 1Z 2E GND 2Y 2Z 1E VCC 1 2 3 4 5 6 7 8 SOT902-1 7 6 5 4 3 2 1 8 independent input or output independent input or output enable input (active HIGH) ground (0 V) independent input or output independent input or output enable input (active HIGH) supply voltage Description 7. Functional description Table 4. Input nE L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Switch OFF-state ON-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK ISK VSW ISW ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input voltage input clamping current switch clamping current switch voltage switch current supply current ground current storage temperature total power dissipation Conditions [1] Min −0.5 −0.5 −50 [2] Max +6.5 +6.5 ±50 VCC + 0.5 ±50 100 +150 250 Unit V V mA mA V mA mA mA °C mW VI < −0.5 V or VI > VCC + 0.5 V VI < −0.5 V or VI > VCC + 0.5 V enable and disable mode VSW > −0.5 V or VSW < VCC + 0.5 V −0.5 −100 −65 Tamb = −40 °C to +125 °C [3] - The minimum input voltage rating may be exceeded if the input current rating is observed. The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 4 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 9. Recommended operating conditions Table 6. Symbol VCC VI VSW Tamb Δt/ΔV Operating conditions Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V [1] [3] [3] [1][2] Conditions Min 1.65 0 0 −40 - Max 5.5 5.5 VCC +125 20 10 Unit V V V °C ns/V ns/V To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no limit for the voltage drop across the switch. For overvoltage tolerant switch voltage capability, refer to 74LVCV2G66. Applies to control signal levels. [2] [3] 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V II IS(OFF) input leakage current OFF-state leakage current ON-state leakage current supply current pin nE; VI = 5.5 V or GND; VCC = 0 V to 5.5 V VCC = 5.5 V; see Figure 8 [2] −40 °C to +85 °C Min 0.65 × VCC 1.7 2.0 0.7 × VCC Typ[1] ±0.1 ±0.1 Max 0.35 × VCC 0.7 0.8 0.3 × VCC ±5 ±5 −40 °C to +125 °C Min 0.65 × VCC 1.7 2.0 0.7 × VCC Max 0.7 0.8 0.3 × VCC ±100 ±200 Unit V V V V V V V μA μA 0.35 × VCC V [2] IS(ON) VCC = 5.5 V; see Figure 9 [2] - ±0.1 ±5 - ±200 μA ICC VI = 5.5 V or GND; VSW = GND or VCC; VCC = 1.65 V to 5.5 V pin nE; VI = VCC − 0.6 V; VSW = GND or VCC; VCC = 5.5 V [2] - 0.1 10 - 200 μA ΔICC additional supply current [2] - 5 500 - 5000 μA 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 5 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI CS(OFF) CS(ON) input capacitance OFF-state capacitance ON-state capacitance Conditions −40 °C to +85 °C Min Typ[1] 2.0 5.0 9.5 Max −40 °C to +125 °C Min Max pF pF pF Unit [1] [2] All typical values are measured at Tamb = 25 °C. These typical values are measured at VCC = 3.3 V. 10.1 Test circuits VCC VIL nE nZ GND nY VIH IS VO VCC nE nZ GND nY IS VI VI VO 001aag488 001aag489 VI = VCC or GND and VO = GND or VCC. VI = VCC or GND and VO = open circuit. Fig 8. Test circuit for measuring OFF-state leakage current Fig 9. Test circuit for measuring ON-state leakage current 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 6 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 11 to Figure 16. Symbol Parameter Conditions VI = GND to VCC; see Figure 10 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(rail) ON resistance (rail) VI = GND; see Figure 10 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V VI = VCC; see Figure 10 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(flat) ON resistance (flatness) VI = GND to VCC ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V [1] [2] Typical values are measured at Tamb = 25 °C and nominal VCC. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. [2] −40 °C to +85 °C Min Typ[1] 34.0 12.0 10.4 7.8 6.2 8.2 7.1 6.9 6.5 5.8 10.4 7.6 7.0 6.1 4.9 26.0 5.0 3.5 2.0 1.5 Max 130 30 25 20 15 18 16 14 12 10 30 20 18 15 10 - −40 °C to +125 °C Min Max 195 45 38 30 23 27 24 21 18 15 45 30 27 23 15 - Unit RON(peak) ON resistance (peak) - Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 7 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 10.3 ON resistance test circuit and graphs 40 RON (Ω) 30 VSW VCC VIH nE nY GND nZ 10 (4) VI ISW (5) mna673 (1) 20 (2) (3) 0 0 001aag490 1 2 3 4 VI (V) 5 RON = VSW/ISW. (1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V. Fig 10. Test circuit for measuring ON resistance Fig 11. Typical ON resistance as a function of input voltage; Tamb = 25 °C 55 RON (Ω) 45 001aaa712 15 RON (Ω) 13 001aaa708 35 (4) (3) (2) (1) 11 (1) (2) 25 9 (3) (4) 15 7 5 0 0.4 0.8 1.2 1.6 VI (V) 2.0 5 0 0.5 1.0 1.5 2.0 VI (V) 2.5 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 12. ON resistance as a function of input voltage; VCC = 1.8 V Fig 13. ON resistance as a function of input voltage; VCC = 2.5 V 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 8 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 13 RON (Ω) 11 001aaa709 10 RON (Ω) 8 001aaa710 (1) (1) (2) 9 (2) (3) 6 (3) 7 (4) (4) 5 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V) 4 0 1 2 3 VI (V) 4 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 14. ON resistance as a function of input voltage; VCC = 2.7 V Fig 15. ON resistance as a function of input voltage; VCC = 3.3 V 7 RON (Ω) 6 001aaa711 5 (1) (2) 4 (3) (4) 3 0 1 2 3 4 VI (V) 5 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 16. ON resistance as a function of input voltage; VCC = 5.0 V 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 9 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 19. Symbol Parameter tpd Conditions [2][3] −40 °C to +85 °C Min Typ[1] Max −40 °C to +125 °C Min Max Unit propagation delay nY to nZ or nZ to nY; see Figure 17 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V [4] 0.8 0.4 0.4 0.3 0.2 2.0 1.2 1.0 0.8 0.6 - 3.0 2.0 1.5 1.5 1.0 ns ns ns ns ns ten enable time nE to nY or nZ; see Figure 18 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.0 1.0 1.0 1.0 1.0 [5] 4.6 2.7 2.7 2.4 1.8 10 5.6 5.0 4.4 3.9 1.0 1.0 1.0 1.0 1.0 13.0 7.5 6.5 6.0 5.0 ns ns ns ns ns tdis disable time nE to nY or nZ; see Figure 18 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.0 1.0 1.0 1.0 1.0 [6] 3.8 2.1 3.5 3.0 2.2 9.0 5.5 6.5 6.0 5.0 1.0 1.0 1.0 1.0 1.0 11.5 7.0 8.5 8.0 6.5 ns ns ns ns ns CPD power dissipation capacitance CL = 50 pF; fi = 10 MHz; VI = GND to VCC VCC = 2.5 V VCC = 3.3 V VCC = 5.0 V - 9.0 11.0 15.7 - - - pF pF pF [1] [2] [3] [4] [5] [6] Typical values are measured at Tamb = 25 °C and nominal VCC. tpd is the same as tPLH and tPHL. Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ{(CL + CS(ON)) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CS(ON) = maximum ON-state switch capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 10 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch Σ{(CL + CS(ON)) × VCC2 × fo} = sum of the outputs. 11.1 Waveforms and test circuit VI nY or nZ input GND t PLH VOH nZ or nY output VOL 001aaa541 VM VM t PHL VM VM Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 17. Input (nY or nZ) to output (nZ or nY) propagation delays VI nE input GND t PLZ VCC nY or nZ output LOW-to-OFF OFF-to-LOW VOL t PHZ output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND switch enabled switch disabled switch enabled 001aaa542 VM t PZL VM VX t PZH nY or nZ Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 18. Enable and disable times Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Output VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VOL + 0.3 V VY VOH − 0.15 V VOH − 0.15 V VOH − 0.3 V VOH − 0.3 V VOH − 0.3 V Supply voltage 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 11 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO 001aae235 Test data is given in Table 11. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 19. Test circuit for measuring switching times Table 11. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2 × VCC 2 × VCC 6V 6V 2 × VCC Supply voltage 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 12 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C. Symbol Parameter THD total harmonic distortion Conditions RL = 10 kΩ; CL = 50 pF; fi = 1 kHz; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 10 kΩ; CL = 50 pF; fi = 10 kHz; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V f(−3dB) −3 dB frequency response RL = 600 Ω; CL = 50 pF; see Figure 21 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 50 Ω; CL = 10 pF; see Figure 21 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 50 Ω; CL = 5 pF; see Figure 21 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V αiso isolation (OFF-state) RL = 600 Ω; CL = 50 pF; fi = 1 MHz; see Figure 22 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 50 Ω; CL = 5 pF; fi = 1 MHz; see Figure 22 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V −37 −37 −37 −37 dB dB dB dB −46 −46 −46 −46 dB dB dB dB > 500 > 500 > 500 > 500 MHz MHz MHz MHz 200 350 410 440 MHz MHz MHz MHz 135 145 150 155 MHz MHz MHz MHz 0.068 0.009 0.008 0.006 % % % % 0.032 0.008 0.006 0.005 % % % % Min Typ Max Unit 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 13 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch Table 12. Additional dynamic characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C. Symbol Parameter Vct crosstalk voltage Conditions between digital inputs and switch; RL = 600 Ω; CL = 50 pF; fi = 1 MHz; tr = tf = 2 ns; see Figure 23 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V Xtalk crosstalk between switches; RL = 600 Ω; CL = 50 pF; fi = 1 MHz; see Figure 24 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V between switches; RL = 50 Ω; CL = 5 pF; fi = 1 MHz; see Figure 24 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V Qinj charge injection CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω; fi = 1 MHz; RL = 1 MΩ; see Figure 25 VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 4.5 V VCC = 5.5 V 3.3 4.1 5.0 6.4 7.5 pC pC pC pC pC −29 −28 −28 dB dB dB dB −56 −56 −56 dB dB dB dB 91 119 205 mV mV mV mV Min Typ Max Unit 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 14 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 11.3 Test circuits VCC VIH nE nY/nZ nZ/nY 0.5VCC RL 10 μF VO CL fi 600 Ω D 001aag492 Test conditions: VCC = 1.65 V: Vi = 1.4 V (p-p). VCC = 2.3 V: Vi = 2 V (p-p). VCC = 3 V: Vi = 2.5 V (p-p). VCC = 4.5 V: Vi = 4 V (p-p). Fig 20. Test circuit for measuring total harmonic distortion VCC VIH 0.1 μF 0.5VCC RL nE nY/nZ nZ/nY VO CL fi 50 Ω dB 001aag491 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB. Fig 21. Test circuit for measuring the frequency response when switch is in ON-state 0.5VCC RL VIL 0.1 μF VCC nE nZ/nY 0.5VCC RL nY/nZ VO CL dB fi 50 Ω 001aag493 Adjust fi voltage to obtain 0 dBm level at input. Fig 22. Test circuit for measuring isolation (OFF-state) 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 15 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch VCC nE nY/nZ G logic input nZ/nY VO RL CL 50 Ω 600 Ω 0.5VCC 0.5VCC 001aag494 Fig 23. Test circuit for measuring crosstalk voltage (between digital inputs and switch) 0.5VCC VIH 0.1 μF Ri 600 Ω fi 50 Ω 1E 1Y or 1Z CHANNEL ON 1Z or 1Y RL CL 50 pF VO1 0.5VCC VIL 2E 2Y or 2Z Ri 600 Ω RL 2Z or 2Y CHANNEL OFF CL 50 pF VO2 001aag496 20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2). Fig 24. Test circuit for measuring crosstalk between switches 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 16 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch VCC nE Rgen nY/nZ nZ/nY RL 1 MΩ CL 0.1 nF VO G logic input Vgen 001aag495 a. Test circuit logic input (nE) off on off VO ΔVO mna675 b. Input and output pulse definitions Qinj = ΔVO × CL. ΔVO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 25. Test circuit for measuring charge injection 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 17 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Fig 26. Package outline SOT505-2 (TSSOP8) 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 18 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 27. Package outline SOT765-1 (VSSOP8) 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 19 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 28. Package outline SOT833-1 (XSON8) 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 20 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 29. Package outline SOT996-2 (XSON8U) 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 21 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 30. Package outline SOT902-1 (XQFN8U) 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 22 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 13. Abbreviations Table 13. Acronym CMOS TTL HBM ESD MM DUT Abbreviations Description Complementary Metal-Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Device Under Test 14. Revision history Table 14. Revision history Release date 20100616 Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet Product data sheet Change notice Supersedes 74LVC2G66 v.4 74LVC2G66 v.3 74LVC2G66 v.2 74LVC2G66 v.1 Document ID 74LVC2G66 v.5 Modifications: 74LVC2G66 v.4 74LVC2G66 v.3 74LVC2G66 v.2 74LVC2G66 v.1 • Conditions for ICC and ΔICC corrected. 20080701 20080310 20070828 20040629 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 23 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 24 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 25 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms and test circuit . . . . . . . . . . . . . . . 11 Additional dynamic characteristics . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 June 2010 Document identifier: 74LVC2G66