74LVC2G74GT

74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 03 — 9 August 2007 Product data sheet 1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2. Features s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) ESD protection: x HBM EIA/JESD22-A114E exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C s s s s s s s s NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC2G74DP 74LVC2G74DC 74LVC2G74GT 74LVC2G74GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP8 VSSOP8 XSON8 XQFN8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm Version SOT505-2 SOT765-1 SOT833-1 SOT902-1 Type number 4. Marking Table 2. Marking Marking code V74 V74 V74 V74 Type number 74LVC2G74DP 74LVC2G74DC 74LVC2G74GT 74LVC2G74GM 5. Functional diagram 7 SD 2 1 D CP SD D CP FF Q RD RD 6 mnb139 Q Q 5 7 1 2 S C1 1D R mnb140 5 Q 3 6 3 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 2 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Q C C C C D C RD C C Q C SD mna421 CP C C Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74LVC2G74 CP D Q GND 1 2 3 4 001aaf642 8 7 6 5 VCC SD RD Q Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74LVC2G74 74LVC2G74 CP 1 8 VCC terminal 1 index area SD 1 VCC 8 7 CP D 2 7 SD RD 2 6 D Q 3 6 RD Q 3 4 5 Q GND GND 4 5 Q 001aaf644 001aaf643 Transparent top view Transparent top view Fig 5. Pin configuration SOT833-1 (XSON8) 74LVC2G74_3 Fig 6. Pin configuration SOT902-1 (XQFN8) © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 3 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 6.2 Pin description Table 3. Symbol Pin description Pin SOT505-2, SOT765-1, SOT833-1 CP D Q GND Q RD SD VCC 1 2 3 4 5 6 7 8 SOT902-1 7 6 5 4 3 2 1 8 clock input (LOW-to-HIGH, edge-triggered) data input complement output ground (0 V) true output asynchronous reset-direct input (active LOW) asynchronous set-direct input (active LOW) supply voltage Description 7. Functional description Table 4. Input SD L H L [1] Function table for asynchronous operation[1] Output RD H L L CP X X X D X X X Q H L H Q L H H H = HIGH voltage level; L = LOW voltage level; X = don’t care. Table 5. Input SD H H [1] Function table for synchronous operation[1] Output RD H H CP ↑ ↑ D L H Qn+1 L H Qn+1 H L H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 4 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Ptot Tstg [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current total power dissipation storage temperature Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [1][2] [1][2] Max +6.5 +6.5 ±50 VCC + 0.5 +6.5 ±50 100 300 +150 Unit V mA V mA V V mA mA mA mW °C VO > VCC or VO < 0 V Active mode Power-down mode VO = 0 V to VCC −0.5 −0.5 −100 Tamb = −40 °C to +125 °C [3] −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 7. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall VCC = 1.65 V to 2.7 V rate VCC = 2.7 V to 5.5 V Active mode Power-down mode; VCC = 0 V Conditions Min 1.65 0 0 0 −40 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V °C ns/V ns/V 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 5 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF ICC ∆ICC CI input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V 0.07 0.12 0.17 0.33 0.39 ±0.1 ±0.1 0.1 5 4.0 0.10 0.45 0.30 0.40 0.55 0.55 ±5 ±10 10 500 V V V V V V µA µA µA µA pF VCC − 0.1 1.2 1.9 2.2 2.3 3.8 1.54 2.15 2.50 2.62 4.11 V V V V V V 0.65 × VCC 1.7 2.0 0.7 × VCC 0.7 0.8 0.3 × VCC V V V V V V V Conditions Min Typ[1] Max Unit 0.35 × VCC V power-off leakage current VI or VO = 5.5 V; VCC = 0 V supply current additional supply current input capacitance 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 6 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF ICC ∆ICC input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V 0.10 0.70 0.45 0.60 0.80 0.80 ±20 ±20 40 5000 V V V V V V µA µA µA µA VCC − 0.1 0.95 1.7 1.9 2.0 3.4 V V V V V V 0.65 × VCC 1.7 2.0 0.7 × VCC 0.7 0.8 0.3 × VCC V V V V V V V Conditions Min Typ[1] Max Unit 0.35 × VCC V power-off leakage current VI or VO = 5.5 V; VCC = 0 V supply current additional supply current [1] All typical values are measured at Tamb = 25 °C. 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 7 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter tpd propagation delay Conditions CP to Q, Q; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V SD to Q, Q; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V RD to Q, Q; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW pulse width CP HIGH or LOW; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V SD and RD LOW; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 6.2 2.7 2.7 2.7 2.0 1.6 6.2 2.7 2.7 2.7 2.0 ns ns ns ns ns 6.2 2.7 2.7 2.7 2.0 1.3 6.2 2.7 2.7 2.7 2.0 ns ns ns ns ns [2] [2] [2] −40 °C to +85 °C Min 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 Typ[1] 6.0 3.5 3.5 3.5 2.5 6.0 3.5 3.5 3.0 2.5 5.0 3.5 3.5 3.0 2.5 Max 13.4 7.1 7.1 5.9 4.1 12.9 7.0 7.0 5.9 4.1 12.9 7.0 7.0 5.9 4.1 −40 °C to +125 °C Min 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 Max 13.4 7.1 7.1 5.9 4.1 12.9 7.0 7.0 5.9 4.1 12.9 7.0 7.0 5.9 4.1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 8 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter trec recovery time Conditions SD or RD; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time D to CP; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V th hold time D to CP; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum frequency CP; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance VI = GND to VCC; VCC = 3.3 V [3] −40 °C to +85 °C Min 1.9 1.4 1.3 +1.2 1.0 2.9 1.7 1.7 1.3 1.1 1.5 1.0 1.0 1.0 1.0 80 175 175 175 200 Typ[1] −3.0 0.5 0.6 280 15 Max - −40 °C to +125 °C Min 1.9 1.4 1.3 +1.2 1.0 2.9 1.7 1.7 1.3 1.1 1.5 1.0 1.0 1.0 1.0 80 175 175 175 200 Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz pF [1] [2] [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 9 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 12. Waveforms tW VM GND 1/fmax VI D input GND th t su t PHL VOH Q output VOL VOH Q output VOL t PLH t PHL mnb141 VI CP input VM th t su t PLH VM VM Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the CP maximum frequency Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Output VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Supply voltage 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 10 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger VI CP input GND t rec VI SD input GND tW VI RD input GND t PLH VOH Q output VOL VOH Q output VOL t PHL t PLH mnb142 VM VM t rec tW VM t PHL VM VM Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP removal time 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 11 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Load circuitry for switching times Table 11. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2VCC 2VCC 6V 6V 2VCC Supply voltage 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 12 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 10. Package outline SOT505-2 (TSSOP8) 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 13 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 11. Package outline SOT765-1 (VSSOP8) 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 14 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 12. Package outline SOT833-1 (XSON8) 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 15 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-16 05-11-25 Fig 13. Package outline SOT902-1 (XQFN8) 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 16 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 14. Abbreviations Table 12. Acronym CMOS TTL HBM ESD MM DUT Abbreviations Description Complementary Metal Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Device Under Test 15. Revision history Table 13. Revision history Release date 20070809 Data sheet status Product data sheet Change notice Supersedes 74LVC2G74_2 Document ID 74LVC2G74_3 Modifications: 74LVC2G74_2 74LVC2G74_1 • • Change of hold time in Section 11 “Dynamic characteristics”. In Section 10 “Static characteristics”, changed conditions for input leakage and supply current. Product data sheet Product data sheet 74LVC2G74_1 - 20061214 20051103 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 17 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 18 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 August 2007 Document identifier: 74LVC2G74_3